// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*
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*/
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#include <dt-bindings/display/media-bus-format.h>
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/ {
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max96712_dphy3_osc0: max96712-dphy3-oscillator@0 {
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compatible = "fixed-clock";
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#clock-cells = <1>;
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clock-frequency = <25000000>;
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clock-output-names = "max96712-dphy3-osc0";
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};
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max96712_dphy3_vcc1v2: max96712-dphy3-vcc1v2 {
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compatible = "regulator-fixed";
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regulator-name = "max96712_dphy3_vcc1v2";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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startup-delay-us = <850>;
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vin-supply = <&vcc5v0_sys>;
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};
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max96712_dphy3_vcc1v8: max96712-dphy3-vcc1v8 {
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compatible = "regulator-fixed";
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regulator-name = "max96712_dphy3_vcc1v8";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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startup-delay-us = <200>;
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vin-supply = <&vcc_3v3_s3>;
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};
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max96712_dphy3_poc: max96712-dphy3-poc {
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compatible = "regulator-fixed";
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regulator-name = "max96712_dphy3_poc";
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regulator-boot-on;
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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enable-active-high;
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gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <1050>;
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off-on-delay-us = <515000>;
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vin-supply = <&vcc12v_dcin>;
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};
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};
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&csi2_dphy1_hw {
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status = "okay";
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};
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&csi2_dphy3 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_dphy3_in_max96712: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&max96712_dphy3_out>;
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data-lanes = <1 2 3 4>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidphy3_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi4_csi2_input>;
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};
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};
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};
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};
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&i2c6 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c6m3_xfer>;
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max96712_dphy3: max96712@29 {
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compatible = "maxim4c,max96712";
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status = "okay";
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reg = <0x29>;
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clock-names = "xvclk";
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clocks = <&max96712_dphy3_osc0 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&max96712_dphy3_pwdn>, <&max96712_dphy3_errb>, <&max96712_dphy3_lock>;
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power-domains = <&power RK3588_PD_VI>;
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rockchip,grf = <&sys_grf>;
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pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
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lock-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
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vcc1v2-supply = <&max96712_dphy3_vcc1v2>;
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vcc1v8-supply = <&max96712_dphy3_vcc1v8>;
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poc-supply = <&max96712_dphy3_poc>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "max96712";
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rockchip,camera-module-lens-name = "max96712";
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port {
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max96712_dphy3_out: endpoint {
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remote-endpoint = <&mipi_dphy3_in_max96712>;
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data-lanes = <1 2 3 4>;
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};
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};
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/* support mode config start */
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support-mode-config {
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status = "okay";
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bus-format = <MEDIA_BUS_FMT_UYVY8_2X8>;
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sensor-width = <1920>;
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sensor-height = <1440>;
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max-fps-numerator = <10000>;
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max-fps-denominator = <300000>;
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bpp = <16>;
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link-freq-idx = <20>;
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vc-array = <0x10 0x20 0x40 0x80>; // VC0~3: bit4~7
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};
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/* support mode config end */
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/* serdes local device start */
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serdes-local-device {
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status = "okay";
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/* GMSL LINK config start */
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gmsl-links {
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status = "okay";
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link-vdd-ldo1-en = <1>;
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link-vdd-ldo2-en = <1>;
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// Link A: link-id = 0
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gmsl-link-config-0 {
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status = "okay";
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link-id = <0>; // Link ID: 0/1/2/3
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link-type = <1>;
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link-rx-rate = <1>;
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link-tx-rate = <0>;
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port {
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max96712_dphy3_link0_in: endpoint {
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remote-endpoint = <&max96712_dphy3_remote0_out>;
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};
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};
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link-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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14 D1 03 00 00 // VGAHiGain
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14 45 00 00 00 // Disable SSC
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];
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};
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};
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// Link B: link-id = 1
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gmsl-link-config-1 {
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status = "okay";
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link-id = <1>; // Link ID: 0/1/2/3
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link-type = <1>;
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link-rx-rate = <1>;
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link-tx-rate = <0>;
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port {
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max96712_dphy3_link1_in: endpoint {
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remote-endpoint = <&max96712_dphy3_remote1_out>;
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};
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};
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link-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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15 D1 03 00 00 // VGAHiGain
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15 45 00 00 00 // Disable SSC
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];
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};
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};
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// Link C: link-id = 2
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gmsl-link-config-2 {
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status = "okay";
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link-id = <2>; // Link ID: 0/1/2/3
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link-type = <1>;
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link-rx-rate = <1>;
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link-tx-rate = <0>;
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port {
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max96712_dphy3_link2_in: endpoint {
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remote-endpoint = <&max96712_dphy3_remote2_out>;
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};
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};
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link-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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16 D1 03 00 00 // VGAHiGain
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16 45 00 00 00 // Disable SSC
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];
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};
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};
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// Link D: link-id = 3
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gmsl-link-config-3 {
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status = "okay";
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link-id = <3>; // Link ID: 0/1/2/3
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link-type = <1>;
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link-rx-rate = <1>;
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link-tx-rate = <0>;
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port {
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max96712_dphy3_link3_in: endpoint {
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remote-endpoint = <&max96712_dphy3_remote3_out>;
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};
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};
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link-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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17 D1 03 00 00 // VGAHiGain
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17 45 00 00 00 // Disable SSC
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];
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};
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};
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};
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/* GMSL LINK config end */
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/* VIDEO PIPE config start */
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video-pipes {
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status = "okay";
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// Video Pipe 0
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video-pipe-config-0 {
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status = "okay";
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pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7
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pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
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link-idx = <0>; // Link A/B/C/D: 0/1/2/3
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pipe-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// Send YUV422, FS, and FE from Video Pipe 0 to Controller 1
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09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
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09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
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// For the following MSB 2 bits = VC, LSB 6 bits = DT
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09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
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09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit
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09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start
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09 10 00 00 00 // DST1 VC = 0, DT = Frame Start
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09 11 01 00 00 // SRC2 VC = 0, DT = Frame End
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09 12 01 00 00 // DST2 VC = 0, DT = Frame End
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];
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};
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};
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// Video Pipe 1
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video-pipe-config-1 {
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status = "okay";
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pipe-id = <1>; // Video Pipe 1: pipe-id = 1
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pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
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link-idx = <1>; // Link A/B/C/D: 0/1/2/3
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pipe-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// Send YUV422, FS, and FE from Video Pipe 1 to Controller 1
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09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
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09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
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// For the following MSB 2 bits = VC, LSB 6 bits = DT
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09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
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09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit
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09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start
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09 50 40 00 00 // DST1 VC = 1, DT = Frame Start
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09 51 01 00 00 // SRC2 VC = 0, DT = Frame End
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09 52 41 00 00 // DST2 VC = 1, DT = Frame End
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];
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};
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};
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// Video Pipe 2
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video-pipe-config-2 {
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status = "okay";
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pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7
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pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
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link-idx = <2>; // Link A/B/C/D: 0/1/2/3
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pipe-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// Send YUV422, FS, and FE from Video Pipe 2 to Controller 1
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09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
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09 AD 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
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// For the following MSB 2 bits = VC, LSB 6 bits = DT
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09 8D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
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09 8E 9e 00 00 // DST0 VC = 2, DT = YUV422 8bit
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09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start
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09 90 80 00 00 // DST1 VC = 2, DT = Frame Start
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09 91 01 00 00 // SRC2 VC = 0, DT = Frame End
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09 92 81 00 00 // DST2 VC = 2, DT = Frame End
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];
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};
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};
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// Video Pipe 3
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video-pipe-config-3 {
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status = "okay";
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pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7
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pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
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link-idx = <3>; // Link A/B/C/D: 0/1/2/3
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pipe-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// Send YUV422, FS, and FE from Video Pipe 3 to Controller 1
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09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings
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09 ED 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
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// For the following MSB 2 bits = VC, LSB 6 bits = DT
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09 CD 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
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09 CE de 00 00 // DST0 VC = 3, DT = YUV422 8bit
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09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start
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09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start
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09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End
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09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End
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];
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};
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};
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};
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/* VIDEO PIPE config end */
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/* MIPI TXPHY config start */
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mipi-txphys {
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status = "okay";
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phy-mode = <0>;
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phy-force-clock-out = <1>;
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phy-force-clk0-en = <1>;
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phy-force-clk3-en = <0>;
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// MIPI TXPHY A: phy-id = 0
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mipi-txphy-config-0 {
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status = "okay";
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phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3
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phy-type = <0>;
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auto-deskew = <0x80>;
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data-lane-num = <4>;
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data-lane-map = <0x4>;
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vc-ext-en = <0>;
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};
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// MIPI TXPHY B: phy-id = 1
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mipi-txphy-config-1 {
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status = "okay";
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phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3
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phy-type = <0>;
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auto-deskew = <0x80>;
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data-lane-num = <4>;
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data-lane-map = <0xe>;
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vc-ext-en = <0>;
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};
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};
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/* MIPI TXPHY config end */
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/* local device extra init sequence */
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extra-init-sequence {
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status = "disabled";
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// common init sequence such as fsync / gpio and so on
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];
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};
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};
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/* serdes local device end */
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/* serdes remote device start */
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serdes-remote-device-0 {
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compatible = "maxim4c,link0,max96717";
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status = "okay";
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remote-id = <0>; // Same as Link ID: 0/1/2/3
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// Serializer i2c 7bit address remap
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ser-i2c-addr-def = <0x40>;
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ser-i2c-addr-map = <0x41>; // 0: disable remap
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// Camera i2c 7bit address remap
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cam-i2c-addr-def = <0x30>;
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cam-i2c-addr-map = <0x31>; // 0: disable remap
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port {
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max96712_dphy3_remote0_out: endpoint {
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remote-endpoint = <&max96712_dphy3_link0_in>;
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};
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};
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remote-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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03 02 10 00 00
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14 17 00 00 00
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14 32 7f 00 00
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];
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};
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};
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serdes-remote-device-1 {
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compatible = "maxim4c,link1,max96717";
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status = "okay";
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remote-id = <1>; // Same as Link ID: 0/1/2/3
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// Serializer i2c 7bit address remap
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ser-i2c-addr-def = <0x40>;
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ser-i2c-addr-map = <0x42>; // 0: disable remap
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// Camera i2c 7bit address remap
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cam-i2c-addr-def = <0x30>;
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cam-i2c-addr-map = <0x32>; // 0: disable remap
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port {
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max96712_dphy3_remote1_out: endpoint {
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remote-endpoint = <&max96712_dphy3_link1_in>;
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};
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};
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remote-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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03 02 10 00 00
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14 17 00 00 00
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14 32 7f 00 00
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];
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};
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};
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serdes-remote-device-2 {
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compatible = "maxim4c,link2,max96717";
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status = "okay";
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remote-id = <2>; // Same as Link ID: 0/1/2/3
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// Serializer i2c 7bit address remap
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ser-i2c-addr-def = <0x40>;
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ser-i2c-addr-map = <0x43>; // 0: disable remap
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// Camera i2c 7bit address remap
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cam-i2c-addr-def = <0x30>;
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cam-i2c-addr-map = <0x33>; // 0: disable remap
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port {
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max96712_dphy3_remote2_out: endpoint {
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remote-endpoint = <&max96712_dphy3_link2_in>;
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};
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};
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remote-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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03 02 10 00 00
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14 17 00 00 00
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14 32 7f 00 00
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];
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};
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};
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serdes-remote-device-3 {
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compatible = "maxim4c,link3,max96717";
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status = "okay";
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remote-id = <3>; // Same as Link ID: 0/1/2/3
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// Serializer i2c 7bit address remap
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ser-i2c-addr-def = <0x40>;
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ser-i2c-addr-map = <0x44>; // 0: disable remap
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// Camera i2c 7bit address remap
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cam-i2c-addr-def = <0x30>;
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cam-i2c-addr-map = <0x34>; // 0: disable remap
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port {
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max96712_dphy3_remote3_out: endpoint {
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remote-endpoint = <&max96712_dphy3_link3_in>;
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};
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};
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remote-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
|
// reg_addr reg_val val_mask delay
|
init-sequence = [
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03 02 10 00 00
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14 17 00 00 00
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14 32 7f 00 00
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];
|
};
|
};
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/* serdes remote device end */
|
};
|
};
|
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&mipi4_csi2 {
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status = "okay";
|
|
ports {
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#address-cells = <1>;
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#size-cells = <0>;
|
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
|
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mipi4_csi2_input: endpoint@1 {
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reg = <1>;
|
remote-endpoint = <&csidphy3_out>;
|
};
|
};
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port@1 {
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reg = <1>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
|
mipi4_csi2_output: endpoint@0 {
|
reg = <0>;
|
remote-endpoint = <&cif_mipi4_in>;
|
};
|
};
|
};
|
};
|
|
&rkcif_mipi_lvds4 {
|
status = "okay";
|
/* parameters for do cif reset detecting:
|
* index0: monitor mode,
|
0 for idle,
|
1 for continue,
|
2 for trigger,
|
3 for hotplug (for nextchip)
|
* index1: the frame id to start timer,
|
min is 2
|
* index2: frame num of monitoring cycle
|
* index3: err time for keep monitoring
|
after finding out err (ms)
|
* index4: csi2 err reference val for resetting
|
*/
|
rockchip,cif-monitor = <3 2 1 1000 5>;
|
|
port {
|
cif_mipi4_in: endpoint {
|
remote-endpoint = <&mipi4_csi2_output>;
|
};
|
};
|
};
|
|
&rkcif {
|
status = "okay";
|
rockchip,android-usb-camerahal-enable;
|
};
|
|
&rkcif_mmu {
|
status = "okay";
|
};
|
|
&pinctrl {
|
max96712-dphy3 {
|
max96712_dphy3_pwdn: max96712-dphy3-pwdn {
|
rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>;
|
};
|
|
max96712_dphy3_errb: max96712-dphy3-errb {
|
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none_smt>;
|
};
|
|
max96712_dphy3_lock: max96712-dphy3-lock {
|
rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none_smt>;
|
};
|
};
|
};
|
