/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Definitions for icm4260x chip.
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*/
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#ifndef __ICM4260X_ACC_H
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#define __ICM4260X_ACC_H
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/* Registers and associated bit definitions */
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/* Bank 0 */
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#define ICM4260X_MISC_1 0x00
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#define ICM4260X_CHIP_CONFIG_REG 0x01
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#define ICM4260X_SIGNAL_PATH_RESET 0x02
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#define ICM4260X_DRIVE_CONFIG_REG1 0x03
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#define ICM4260X_DRIVE_CONFIG_REG2 0x04
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#define ICM4260X_DRIVE_CONFIG_REG3 0x05
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#define ICM4260X_INT_CONFIG_REG 0x06
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#define ICM4260X_ODRGRID0 0x07
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#define ICM4260X_ODRGRID1 0x08
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#define ICM4260X_TEMP_DATA0 0x09
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#define ICM4260X_TEMP_DATA1 0x0a
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#define ICM4260X_ACCEL_DATA_X0 0x0b
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#define ICM4260X_ACCEL_DATA_X1 0x0c
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#define ICM4260X_ACCEL_DATA_Y0 0x0d
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#define ICM4260X_ACCEL_DATA_Y1 0x0e
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#define ICM4260X_ACCEL_DATA_Z0 0x0f
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#define ICM4260X_ACCEL_DATA_Z1 0x10
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#define ICM4260X_GYRO_DATA_X0 0x11
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#define ICM4260X_GYRO_DATA_X1 0x12
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#define ICM4260X_GYRO_DATA_Y0 0x13
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#define ICM4260X_GYRO_DATA_Y1 0x14
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#define ICM4260X_GYRO_DATA_Z0 0x15
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#define ICM4260X_GYRO_DATA_Z1 0x16
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#define ICM4260X_TMST_FSYNC1 0x17
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#define ICM4260X_TMST_FSYNC2 0x18
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#define ICM4260X_ODR_LP_STATUS 0x19
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#define ICM4260X_PWR_MGMT_0 0x1f
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#define ICM4260X_GYRO_CONFIG0 0x20
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#define ICM4260X_ACCEL_CONFIG0 0x21
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#define ICM4260X_TEMP_CONFIG0 0x22
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#define ICM4260X_GYRO_CONFIG1 0x23
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#define ICM4260X_ACCEL_CONFIG1 0x24
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#define ICM4260X_APEX_CONFIG0 0x25
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#define ICM4260X_APEX_CONFIG1 0x26
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#define ICM4260X_WOM_CONFIG 0x27
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#define ICM4260X_FIFO_CONFIG1 0x28
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#define ICM4260X_FIFO_CONFIG2 0x29
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#define ICM4260X_FIFO_CONFIG3 0x2a
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#define ICM4260X_INT_SOURCE0 0x2b
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#define ICM4260X_INT_SOURCE1 0x2c
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#define ICM4260X_INT_SOURCE3 0x2d
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#define ICM4260X_INT_SOURCE4 0x2e
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#define ICM4260X_FIFO_LOST_PKT0 0x2f
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#define ICM4260X_FIFO_LOST_PKT1 0x30
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#define ICM4260X_APEX_DATA0 0x31
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#define ICM4260X_APEX_DATA1 0x32
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#define ICM4260X_APEX_DATA2 0x33
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#define ICM4260X_APEX_DATA3 0x34
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#define ICM4260X_INTF_CONFIG0 0x35
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#define ICM4260X_INTF_CONFIG1 0x36
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#define ICM4260X_INT_STATUS_DRDY 0x39
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#define ICM4260X_INT_STATUS 0x3a
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#define ICM4260X_INT_STATUS2 0x3b
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#define ICM4260X_INT_STATUS3 0x3c
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#define ICM4260X_FIFO_BYTE_COUNT1 0x3d
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#define ICM4260X_FIFO_BYTE_COUNT2 0x3e
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#define ICM4260X_FIFO_DATA_REG 0x3f
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#define ICM4260X_S4S_GYRO_TPH1 0x40
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#define ICM4260X_S4S_GYRO_TPH2 0x41
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#define ICM4260X_S4S_ACCEL_TPH1 0x42
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#define ICM4260X_S4S_ACCEL_TPH2 0x43
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#define ICM4260X_S4S_RR 0x44
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#define ICM4260X_GYR_BIAS_CFG1 0x46
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#define ICM4260X_WHO_AM_I 0x75
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#define ICM4260X_S4S_ST 0x76
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#define ICM4260X_S4S_ST_CLONE 0x77
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#define ICM4260X_S4S_DT 0x78
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#define ICM4260X_BLK_SEL_W 0x79
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#define ICM4260X_MADDR_W 0x7a
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#define ICM4260X_M_W 0x7b
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#define ICM4260X_BLK_SEL_R 0x7c
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#define ICM4260X_MADDR_R 0x7d
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#define ICM4260X_M_R 0x7e
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/* MREG_TOP1 */
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#define ICM4260X_TMST_CONFIG1_MREG_TOP1 0x00
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#define ICM4260X_FIFO_CONFIG5_MREG_TOP1 0x01
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#define ICM4260X_FIFO_CONFIG6_MREG_TOP1 0x02
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#define ICM4260X_FSYNC_CONFIG_MREG_TOP1 0x03
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#define ICM4260X_INT_CONFIG0_MREG_TOP1 0x04
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#define ICM4260X_INT_CONFIG1_MREG_TOP1 0x05
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#define ICM4260X_AFSR_CONFIG0_MREG_TOP1 0x07
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#define ICM4260X_AFSR_CONFIG1_MREG_TOP1 0x08
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#define ICM4260X_TBC_RCOSC_MREG_TOP1 0x0d
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#define ICM4260X_TBC_PLL_MREG_TOP1 0x0e
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#define ICM4260X_ST_CONFIG_MREG_TOP1 0x13
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#define ICM4260X_SELFTEST_MREG_TOP1 0x14
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#define ICM4260X_PADS_CONFIG3_MREG_TOP1 0x17
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#define ICM4260X_TEMP_CONFIG1_MREG_TOP1 0x1c
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#define ICM4260X_TEMP_CONFIG3_MREG_TOP1 0x1e
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#define ICM4260X_S4S_CONFIG1_MREG_TOP1 0x1f
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#define ICM4260X_S4S_CONFIG2_MREG_TOP1 0x20
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#define ICM4260X_S4S_FREQ_RATIO1_MREG_TOP1 0x21
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#define ICM4260X_S4S_FREQ_RATIO2_MREG_TOP1 0x22
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#define ICM4260X_INTF_CONFIG6_MREG_TOP1 0x23
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#define ICM4260X_INTF_CONFIG10_MREG_TOP1 0x25
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#define ICM4260X_INTF_CONFIG7_MREG_TOP1 0x28
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#define ICM4260X_OTP_CONFIG_MREG_TOP1 0x2b
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#define ICM4260X_INT_SOURCE6_MREG_TOP1 0x2f
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#define ICM4260X_INT_SOURCE7_MREG_TOP1 0x30
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#define ICM4260X_INT_SOURCE8_MREG_TOP1 0x31
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#define ICM4260X_INT_SOURCE9_MREG_TOP1 0x32
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#define ICM4260X_INT_SOURCE10_MREG_TOP1 0x33
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#define ICM4260X_GYRO_PWR_CFG0_MREG_TOP1 0x38
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#define ICM4260X_ACCEL_CP_CFG0_MREG_TOP1 0x39
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#define ICM4260X_APEX_CONFIG2_MREG_TOP1 0x44
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#define ICM4260X_APEX_CONFIG3_MREG_TOP1 0x45
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#define ICM4260X_APEX_CONFIG4_MREG_TOP1 0x46
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#define ICM4260X_APEX_CONFIG5_MREG_TOP1 0x47
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#define ICM4260X_APEX_CONFIG9_MREG_TOP1 0x48
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#define ICM4260X_APEX_CONFIG10_MREG_TOP1 0x49
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#define ICM4260X_APEX_CONFIG11_MREG_TOP1 0x4a
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#define ICM4260X_APEX_CONFIG12_MREG_TOP1 0x67
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#define ICM4260X_ACCEL_WOM_X_THR_MREG_TOP1 0x4b
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#define ICM4260X_ACCEL_WOM_Y_THR_MREG_TOP1 0x4c
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#define ICM4260X_ACCEL_WOM_Z_THR_MREG_TOP1 0x4d
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#define ICM4260X_GOS_USER0_MREG_TOP1 0x4e
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#define ICM4260X_GOS_USER1_MREG_TOP1 0x4f
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#define ICM4260X_GOS_USER2_MREG_TOP1 0x50
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#define ICM4260X_GOS_USER3_MREG_TOP1 0x51
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#define ICM4260X_GOS_USER4_MREG_TOP1 0x52
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#define ICM4260X_GOS_USER5_MREG_TOP1 0x53
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#define ICM4260X_GOS_USER6_MREG_TOP1 0x54
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#define ICM4260X_GOS_USER7_MREG_TOP1 0x55
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#define ICM4260X_GOS_USER8_MREG_TOP1 0x56
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#define ICM4260X_ST_STATUS1_MREG_TOP1 0x63
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#define ICM4260X_ST_STATUS2_MREG_TOP1 0x64
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/* MMEM_TOP */
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#define ICM4260X_XA_ST_DATA_MMEM_TOP 0x5000
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#define ICM4260X_YA_ST_DATA_MMEM_TOP 0x5001
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#define ICM4260X_ZA_ST_DATA_MMEM_TOP 0x5002
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#define ICM4260X_XG_ST_DATA_MMEM_TOP 0x5003
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#define ICM4260X_YG_ST_DATA_MMEM_TOP 0x5004
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#define ICM4260X_ZG_ST_DATA_MMEM_TOP 0x5005
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/* MREG_OTP */
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#define ICM4260X_OTP_CTRL7_MREG_OTP 0x2806
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/* Bank0 REG_GYRO_CONFIG0/REG_ACCEL_CONFIG0 */
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#define SHIFT_GYRO_FS_SEL 5
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#define SHIFT_ACCEL_FS_SEL 5
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#define SHIFT_ODR_CONF 0
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#define BIT_GYRO_FSR 0x60
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#define BIT_GYRO_ODR 0x0F
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#define BIT_ACCEL_FSR 0x60
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#define ACCEL_FS_SEL 3 //(-2G, +2G)
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#define GYRO_FS_SEL 3 //00~11:2000dps\1000dps\500dps\250dps
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#define BIT_ACCEL_ODR 0x0F
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#define BIT_SENSOR_ODR_800HZ 0x06
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#define BIT_SENSOR_ODR_400HZ 0x07
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#define BIT_SENSOR_ODR_200HZ 0x08
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#define BIT_SENSOR_ODR_100HZ 0x09
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#define BIT_SENSOR_ODR_50HZ 0x0A
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#define BIT_SENSOR_ODR_25HZ 0x0B
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#define BIT_SENSOR_ODR_12HZ 0x0C
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#define BIT_SENSOR_ODR_6HZ 0x0D
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#define BIT_SENSOR_ODR_3HZ 0x0E
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/* Bank0 REG_GYRO_CONFIG1 */
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#define BIT_GYR_UI_FLT_BW_BYPASS 0x00
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#define BIT_GYR_UI_FLT_BW_180HZ 0x01
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#define BIT_GYR_UI_FLT_BW_121HZ 0x02
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#define BIT_GYR_UI_FLT_BW_73HZ 0x03
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#define BIT_GYR_UI_FLT_BW_53HZ 0x04
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#define BIT_GYR_UI_FLT_BW_34HZ 0x05
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#define BIT_GYR_UI_FLT_BW_25HZ 0x06
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#define BIT_GYR_UI_FLT_BW_16HZ 0x07
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#define BIT_GYR_UI_AVG_IND_2X 0x00
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#define BIT_GYR_UI_AVG_IND_4X 0x10
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#define BIT_GYR_UI_AVG_IND_8X 0x20
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#define BIT_GYR_UI_AVG_IND_16X 0x30
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#define BIT_GYR_UI_AVG_IND_32X 0x40
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#define BIT_GYR_UI_AVG_IND_64X 0x50
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/* Bank0 REG_ACCEL_CONFIG1 */
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#define BIT_ACC_FILT_BW_IND_BYPASS 0x00
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#define BIT_ACC_FILT_BW_IND_180HZ 0x01
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#define BIT_ACC_FILT_BW_IND_121HZ 0x02
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#define BIT_ACC_FILT_BW_IND_73HZ 0x03
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#define BIT_ACC_FILT_BW_IND_53HZ 0x04
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#define BIT_ACC_FILT_BW_IND_34HZ 0x05
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#define BIT_ACC_FILT_BW_IND_25HZ 0x06
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#define BIT_ACC_FILT_BW_IND_16HZ 0x07
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#define BIT_ACC_UI_AVG_IND_2X 0x00
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#define BIT_ACC_UI_AVG_IND_4X 0x10
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#define BIT_ACC_UI_AVG_IND_8X 0x20
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#define BIT_ACC_UI_AVG_IND_16X 0x30
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#define BIT_ACC_UI_AVG_IND_32X 0x40
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#define BIT_ACC_UI_AVG_IND_64X 0x50
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/* Bank0 REG_INT_CONFIG_REG */
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#define SHIFT_INT1_MODE 0x02
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#define SHIFT_INT1_DRIVE_CIRCUIT 0x01
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#define SHIFT_INT1_POLARITY 0x00
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/* Bank0 REG_PWR_MGMT_0 */
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#define BIT_ACCEL_MODE_OFF 0x00
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#define BIT_ACCEL_MODE_LPM 0x02
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#define BIT_ACCEL_MODE_LNM 0x03
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#define BIT_ACCEL_MODE_MASK 0x03
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#define BIT_GYRO_MODE_OFF 0x00
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#define BIT_GYRO_MODE_STBY 0x04
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#define BIT_GYRO_MODE_LPM 0x08
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#define BIT_GYRO_MODE_LNM 0x0c
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#define BIT_GYRO_MODE_MASK 0x0c
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#define BIT_IDLE 0x10
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#define BIT_ACCEL_LP_CLK_SEL 0x80
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/* Bank0 REG_SIGNAL_PATH_RESET */
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#define BIT_FIFO_FLUSH 0x04
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#define BIT_SOFT_RESET_CHIP_CONFIG 0x10
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/* Bank0 REG_INTF_CONFIG0 */
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#define BIT_SIFS_CFG_I2C_ONLY 0x02
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#define BIT_SIFS_CFG_SPI_ONLY 0x03
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#define BIT_SENSOR_DATA_ENDIAN 0x10
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#define BIT_FIFO_COUNT_ENDIAN 0x20
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#define BIT_FIFO_COUNT_FORMAT 0x40
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#define BIT_FIFO_SREG_INVALID_IND_DIS 0x80
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/* Bank0 REG_INTF_CONFIG1 */
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#define BIT_CLK_SEL_RC 0x00
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#define BIT_CLK_SEL_PLL 0x01
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#define BIT_CLK_SEL_DIS 0x03
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#define BIT_I3C_DDR_EN 0x04
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#define BIT_I3C_SDR_EN 0x08
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#define BIT_GYRO_AFSR_MODE_LFS 0x00
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#define BIT_GYRO_AFSR_MODE_HFS 0x20
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#define BIT_GYRO_AFSR_MODE_DYN 0x40
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/* Bank0 REG_FIFO_CONFIG1 */
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#define BIT_FIFO_MODE_NO_BYPASS 0x00
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#define BIT_FIFO_MODE_BYPASS 0x01
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#define BIT_FIFO_MODE_STREAM 0x00
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#define BIT_FIFO_MODE_STOPFULL 0x02
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/* Bank 0 REG_INT_SOURCE0 */
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#define BIT_INT_AGC_RDY_INT1_EN 0x01
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#define BIT_INT_FIFO_FULL_INT1_EN 0x02
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#define BIT_INT_FIFO_THS_INT1_EN 0x04
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#define BIT_INT_DRDY_INT_EN 0x08
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#define BIT_INT_RESET_DONE_INT1_EN 0x10
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#define BIT_INT_PLL_RDY_INT1_EN 0x20
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#define BIT_INT_FSYNC_INT1_EN 0x40
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#define BIT_INT_ST_DONE_INT1_EN 0x80
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/* Bank 0 REG_INT_SOURCE1 */
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#define BIT_INT_WOM_X_INT1_EN 0x01
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#define BIT_INT_WOM_Y_INT1_EN 0x02
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#define BIT_INT_WOM_Z_INT1_EN 0x04
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#define BIT_INT_WOM_XYZ_INT1_EN (BIT_INT_WOM_X_INT1_EN | \
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BIT_INT_WOM_Y_INT1_EN | BIT_INT_WOM_Z_INT1_EN)
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#define BIT_INT_SMD_INT1_EN 0x08
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#define BIT_INT_I3C_PROTCL_ERR_INT1_EN 0x40
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/* Bank0 REG_INT_STATUS_DRDY */
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#define BIT_INT_STATUS_DRDY 0x01
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/* Bank0 REG_INT_STATUS */
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#define BIT_INT_STATUS_AGC_RDY 0x01
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#define BIT_INT_STATUS_FIFO_FULL 0x02
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#define BIT_INT_STATUS_FIFO_THS 0x04
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#define BIT_INT_STATUS_RESET_DONE 0x10
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#define BIT_INT_STATUS_PLL_RDY 0x20
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#define BIT_INT_STATUS_FSYNC 0x40
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#define BIT_INT_STATUS_ST_DONE 0x80
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/* Bank0 REG_INT_STATUS2 */
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#define BIT_INT_STATUS_WOM_Z 0x01
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#define BIT_INT_STATUS_WOM_Y 0x02
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#define BIT_INT_STATUS_WOM_X 0x04
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#define BIT_INT_STATUS_WOM_XYZ (BIT_INT_STATUS_WOM_X | \
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BIT_INT_STATUS_WOM_Y | BIT_INT_STATUS_WOM_Z)
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#define BIT_INT_STATUS_SMD 0x08
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/* Bank 0 REG_INT_STATUS3 */
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#define BIT_INT_STATUS_LOWG_DET 0x02
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#define BIT_INT_STATUS_FF_DET 0x04
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#define BIT_INT_STATUS_TILT_DET 0x08
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#define BIT_INT_STATUS_STEP_CNT_OVFL 0x10
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#define BIT_INT_STATUS_STEP_DET 0x20
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/* Bank0 REG_WOM_CONFIG */
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#define BIT_WOM_EN_OFF 0x00
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#define BIT_WOM_EN_ON 0x01
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#define BIT_WOM_MODE_INITIAL 0x00
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#define BIT_WOM_MODE_PREV 0x02
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#define BIT_WOM_INT_MODE_OR 0x00
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#define BIT_WOM_INT_MODE_AND 0x04
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#define BIT_WOM_INT_DUR_LEGACY 0x00
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#define BIT_WOM_INT_DUR_2ND 0x08
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#define BIT_WOM_INT_DUR_3RD 0x10
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#define BIT_WOM_INT_DUR_4TH 0x18
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/* Bank0 REG_APEX_CONFIG0 */
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#define BIT_DMP_SRAM_RESET_APEX 0x01
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#define BIT_DMP_INIT_EN 0x04
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#define BIT_DMP_POWER_SAVE_EN 0x08
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/* Bank0 REG_APEX_CONFIG1 */
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#define BIT_DMP_ODR_25HZ 0x00
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#define BIT_DMP_ODR_50HZ 0x02
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#define BIT_DMP_ODR_100HZ 0x03
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#define BIT_DMP_PEDO_EN 0x08
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#define BIT_DMP_TILT_EN 0x10
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#define BIT_DMP_FF_EN 0x20
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#define BIT_DMP_SMD_EN 0x40
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/* REG_OTP_CONFIG_MREG_TOP1 */
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#define BIT_OTP_COPY_NORMAL 0x04
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#define BIT_OTP_COPY_ST_DATA 0x0C
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#define OTP_COPY_MODE_MASK 0x0C
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/* REG_INT_SOURCE6_MREG_TOP1 */
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#define BIT_INT_TLT_DET_INT1_EN 0x08
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#define BIT_INT_STEP_CNT_OVFL_INT1_EN 0x10
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#define BIT_INT_STEP_DET_INT1_EN 0x20
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#define BIT_INT_LOWG_INT1_EN 0x40
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#define BIT_INT_FF_INT1_EN 0x80
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/* REG_TMST_CONFIG1_MREG_TOP1 */
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#define BIT_TMST_EN 0x01
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#define BIT_TMST_FSYNC_EN 0x02
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#define BIT_TMST_DELTA_EN 0x04
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#define BIT_TMST_RESOL 0x08
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#define BIT_TMST_ON_SREG_EN 0x10
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#define BIT_ODR_EN_WITHOUT_SENSOR 0x40
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/* REG_FIFO_CONFIG5_MREG_TOP1 */
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#define BIT_FIFO_ACCEL_EN 0x01
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#define BIT_FIFO_GYRO_EN 0x02
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#define BIT_FIFO_TMST_FSYNC_EN 0x04
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#define BIT_FIFO_HIRES_EN 0x08
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#define BIT_RESUME_PARTIAL_RD 0x10
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#define BIT_WM_GT_TH 0x20
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/* REG_SELFTEST_MREG_TOP1 */
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#define BIT_EN_AX_ST 0x01
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#define BIT_EN_AY_ST 0x02
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#define BIT_EN_AZ_ST 0x04
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#define BIT_EN_GX_ST 0x08
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#define BIT_EN_GY_ST 0x10
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#define BIT_EN_GZ_ST 0x20
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#define BIT_ACCEL_ST_EN 0x40
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#define BIT_GYRO_ST_EN 0x80
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/* REG_ST_CONFIG_MREG_TOP1 */
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#define BIT_PD_ACCEL_CP45_ST_REG 0x80
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#define SHIFT_GYRO_ST_LIM 0
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#define SHIFT_ACCEL_ST_LIM 3
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#define SHIFT_ST_NUM_SAMPLE 6
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/* REG_ST_STATUS1_MREG_TOP1 */
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#define BIT_DMP_AX_ST_PASS 0x02
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#define BIT_DMP_AY_ST_PASS 0x04
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#define BIT_DMP_AZ_ST_PASS 0x08
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#define BIT_DMP_ACCEL_ST_DONE 0x10
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#define BIT_DMP_ACCEL_ST_PASS 0x20
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/* REG_ST_STATUS2_MREG_TOP1 */
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#define BIT_DMP_GX_ST_PASS 0x02
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#define BIT_DMP_GY_ST_PASS 0x04
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#define BIT_DMP_GZ_ST_PASS 0x08
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#define BIT_DMP_GYRO_ST_DONE 0x10
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#define BIT_DMP_GYRO_ST_PASS 0x20
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#define BIT_DMP_ST_INCOMPLETE 0x40
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/* REG_OTP_CTRL7_MREG_OTP */
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#define BIT_OTP_RELOAD 0x08
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#define BIT_OTP_PWR_DOWN 0x02
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/* fifo data packet header */
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#define BIT_FIFO_HEAD_MSG 0x80
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#define BIT_FIFO_HEAD_ACCEL 0x40
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#define BIT_FIFO_HEAD_GYRO 0x20
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#define BIT_FIFO_HEAD_20 0x10
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#define BIT_FIFO_HEAD_TMSP_ODR 0x08
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#define BIT_FIFO_HEAD_TMSP_NO_ODR 0x04
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#define BIT_FIFO_HEAD_TMSP_FSYNC 0x0C
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#define BIT_FIFO_HEAD_ODR_ACCEL 0x02
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#define BIT_FIFO_HEAD_ODR_GYRO 0x01
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/* data definitions */
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#define FIFO_PACKET_BYTE_SINGLE 8
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#define FIFO_PACKET_BYTE_6X 16
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#define FIFO_PACKET_BYTE_HIRES 20
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#define FIFO_COUNT_BYTE 2
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/* sensor startup time */
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#define INV_ICM43600_GYRO_START_TIME 100
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#define INV_ICM43600_ACCEL_START_TIME 100
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/* sensor stop time */
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#define INV_ICM43600_GYRO_STOP_TIME 20
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/* M-reg access wait tile */
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#define INV_ICM42607_MCLK_WAIT_US 20
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#define INV_ICM42607_BLK_SEL_WAIT_US 10
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#define INV_ICM42607_MADDR_WAIT_US 10
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#define INV_ICM42607_M_RW_WAIT_US 10
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/* temperature sensor */
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#define TEMP_SCALE 100 /* scale by 100 */
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#define TEMP_LSB_PER_DEG 2 /* 2LSB=1degC */
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#define TEMP_OFFSET 25 /* 25 degC */
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/*
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* INT configurations
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* Polarity: 0 -> Active Low, 1 -> Active High
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* Drive circuit: 0 -> Open Drain, 1 -> Push-Pull
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* Mode: 0 -> Pulse, 1 -> Latch
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*/
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#define INT_POLARITY 1
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#define INT_DRIVE_CIRCUIT 1
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#define INT_MODE 0
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#define ICM42607_DEVICE_ID 0x61
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#define ICM4260X_PRECISION 16
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#define ICM42607_ADDR 0x68
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#endif
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