/* SPDX-License-Identifier: MIT */
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#ifndef __NVBIOS_M0203_H__
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#define __NVBIOS_M0203_H__
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struct nvbios_M0203T {
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#define M0203T_TYPE_RAMCFG 0x00
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u8 type;
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u16 pointer;
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};
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u32 nvbios_M0203Te(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
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u32 nvbios_M0203Tp(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
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struct nvbios_M0203T *);
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struct nvbios_M0203E {
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#define M0203E_TYPE_DDR2 0x0
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#define M0203E_TYPE_DDR3 0x1
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#define M0203E_TYPE_GDDR3 0x2
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#define M0203E_TYPE_GDDR5 0x3
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#define M0203E_TYPE_HBM2 0x6
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#define M0203E_TYPE_GDDR5X 0x8
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#define M0203E_TYPE_GDDR6 0x9
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#define M0203E_TYPE_SKIP 0xf
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u8 type;
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u8 strap;
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u8 group;
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};
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u32 nvbios_M0203Ee(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr);
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u32 nvbios_M0203Ep(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr,
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struct nvbios_M0203E *);
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u32 nvbios_M0203Em(struct nvkm_bios *, u8 ramcfg, u8 *ver, u8 *hdr,
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struct nvbios_M0203E *);
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#endif
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