/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_MACH_LOONGSON64_CPUCFG_EMUL_H_
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#define _ASM_MACH_LOONGSON64_CPUCFG_EMUL_H_
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#include <asm/cpu-info.h>
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#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
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#include <loongson_regs.h>
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#define LOONGSON_FPREV_MASK 0x7
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void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c);
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static inline bool loongson3_cpucfg_emulation_enabled(struct cpuinfo_mips *c)
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{
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/* All supported cores have non-zero LOONGSON_CFG1 data. */
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return c->loongson3_cpucfg_data[0] != 0;
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}
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static inline u32 loongson3_cpucfg_read_synthesized(struct cpuinfo_mips *c,
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__u64 sel)
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{
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switch (sel) {
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case LOONGSON_CFG0:
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return c->processor_id;
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case LOONGSON_CFG1:
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case LOONGSON_CFG2:
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case LOONGSON_CFG3:
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return c->loongson3_cpucfg_data[sel - 1];
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case LOONGSON_CFG4:
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case LOONGSON_CFG5:
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/* CPUCFG selects 4 and 5 are related to the input clock
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* signal.
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*
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* Unimplemented for now.
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*/
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return 0;
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case LOONGSON_CFG6:
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/* CPUCFG select 6 is for the undocumented Safe Extension. */
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return 0;
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case LOONGSON_CFG7:
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/* CPUCFG select 7 is for the virtualization extension.
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* We don't know if the two currently known features are
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* supported on older cores according to the public
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* documentation, so leave this at zero.
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*/
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return 0;
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}
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/*
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* Return 0 for unrecognized CPUCFG selects, which is real hardware
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* behavior observed on Loongson 3A R4.
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*/
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return 0;
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}
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#else
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static inline void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
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{
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}
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static inline bool loongson3_cpucfg_emulation_enabled(struct cpuinfo_mips *c)
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{
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return false;
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}
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static inline u32 loongson3_cpucfg_read_synthesized(struct cpuinfo_mips *c,
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__u64 sel)
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{
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return 0;
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}
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#endif
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#endif /* _ASM_MACH_LOONGSON64_CPUCFG_EMUL_H_ */
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