/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* ACPI wakeup real mode startup stub
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*/
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#include <linux/linkage.h>
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#include <asm/segment.h>
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#include <asm/msr-index.h>
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#include <asm/page_types.h>
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#include <asm/pgtable_types.h>
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#include <asm/processor-flags.h>
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#include "realmode.h"
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#include "wakeup.h"
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.code16
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/* This should match the structure in wakeup.h */
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.section ".data", "aw"
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.balign 16
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GLOBAL(wakeup_header)
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video_mode: .short 0 /* Video mode number */
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pmode_entry: .long 0
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pmode_cs: .short __KERNEL_CS
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pmode_cr0: .long 0 /* Saved %cr0 */
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pmode_cr3: .long 0 /* Saved %cr3 */
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pmode_cr4: .long 0 /* Saved %cr4 */
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pmode_efer: .quad 0 /* Saved EFER */
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pmode_gdt: .quad 0
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pmode_misc_en: .quad 0 /* Saved MISC_ENABLE MSR */
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pmode_behavior: .long 0 /* Wakeup behavior flags */
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realmode_flags: .long 0
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real_magic: .long 0
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signature: .long WAKEUP_HEADER_SIGNATURE
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END(wakeup_header)
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.text
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.code16
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.balign 16
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ENTRY(wakeup_start)
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cli
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cld
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LJMPW_RM(3f)
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3:
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/* Apparently some dimwit BIOS programmers don't know how to
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program a PM to RM transition, and we might end up here with
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junk in the data segment descriptor registers. The only way
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to repair that is to go into PM and fix it ourselves... */
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movw $16, %cx
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lgdtl %cs:wakeup_gdt
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movl %cr0, %eax
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orb $X86_CR0_PE, %al
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movl %eax, %cr0
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ljmpw $8, $2f
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2:
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movw %cx, %ds
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movw %cx, %es
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movw %cx, %ss
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movw %cx, %fs
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movw %cx, %gs
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andb $~X86_CR0_PE, %al
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movl %eax, %cr0
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LJMPW_RM(3f)
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3:
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/* Set up segments */
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movw %cs, %ax
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movw %ax, %ss
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movl $rm_stack_end, %esp
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %fs
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movw %ax, %gs
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lidtl wakeup_idt
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/* Clear the EFLAGS */
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pushl $0
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popfl
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/* Check header signature... */
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movl signature, %eax
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cmpl $WAKEUP_HEADER_SIGNATURE, %eax
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jne bogus_real_magic
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/* Check we really have everything... */
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movl end_signature, %eax
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cmpl $REALMODE_END_SIGNATURE, %eax
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jne bogus_real_magic
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/* Call the C code */
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calll main
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/* Restore MISC_ENABLE before entering protected mode, in case
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BIOS decided to clear XD_DISABLE during S3. */
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movl pmode_behavior, %edi
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btl $WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE, %edi
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jnc 1f
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movl pmode_misc_en, %eax
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movl pmode_misc_en + 4, %edx
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movl $MSR_IA32_MISC_ENABLE, %ecx
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wrmsr
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1:
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/* Do any other stuff... */
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#ifndef CONFIG_64BIT
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/* This could also be done in C code... */
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movl pmode_cr3, %eax
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movl %eax, %cr3
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btl $WAKEUP_BEHAVIOR_RESTORE_CR4, %edi
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jnc 1f
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movl pmode_cr4, %eax
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movl %eax, %cr4
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1:
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btl $WAKEUP_BEHAVIOR_RESTORE_EFER, %edi
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jnc 1f
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movl pmode_efer, %eax
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movl pmode_efer + 4, %edx
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movl $MSR_EFER, %ecx
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wrmsr
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1:
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lgdtl pmode_gdt
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/* This really couldn't... */
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movl pmode_entry, %eax
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movl pmode_cr0, %ecx
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movl %ecx, %cr0
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ljmpl $__KERNEL_CS, $pa_startup_32
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/* -> jmp *%eax in trampoline_32.S */
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#else
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jmp trampoline_start
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#endif
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bogus_real_magic:
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1:
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hlt
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jmp 1b
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.section ".rodata","a"
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/*
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* Set up the wakeup GDT. We set these up as Big Real Mode,
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* that is, with limits set to 4 GB. At least the Lenovo
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* Thinkpad X61 is known to need this for the video BIOS
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* initialization quirk to work; this is likely to also
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* be the case for other laptops or integrated video devices.
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*/
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.balign 16
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GLOBAL(wakeup_gdt)
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.word 3*8-1 /* Self-descriptor */
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.long pa_wakeup_gdt
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.word 0
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.word 0xffff /* 16-bit code segment @ real_mode_base */
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.long 0x9b000000 + pa_real_mode_base
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.word 0x008f /* big real mode */
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.word 0xffff /* 16-bit data segment @ real_mode_base */
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.long 0x93000000 + pa_real_mode_base
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.word 0x008f /* big real mode */
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END(wakeup_gdt)
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.section ".rodata","a"
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.balign 8
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/* This is the standard real-mode IDT */
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.balign 16
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GLOBAL(wakeup_idt)
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.word 0xffff /* limit */
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.long 0 /* address */
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.word 0
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END(wakeup_idt)
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