/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* SGI UV IRQ functions
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*
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* Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
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*/
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#include <linux/export.h>
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#include <linux/rbtree.h>
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#include <linux/slab.h>
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#include <linux/irq.h>
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#include <asm/irqdomain.h>
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#include <asm/apic.h>
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#include <asm/uv/uv_irq.h>
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#include <asm/uv/uv_hub.h>
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/* MMR offset and pnode of hub sourcing interrupts for a given irq */
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struct uv_irq_2_mmr_pnode {
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unsigned long offset;
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int pnode;
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};
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static void uv_program_mmr(struct irq_cfg *cfg, struct uv_irq_2_mmr_pnode *info)
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{
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unsigned long mmr_value;
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struct uv_IO_APIC_route_entry *entry;
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BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) !=
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sizeof(unsigned long));
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mmr_value = 0;
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entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
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entry->vector = cfg->vector;
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entry->delivery_mode = apic->irq_delivery_mode;
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entry->dest_mode = apic->irq_dest_mode;
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entry->polarity = 0;
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entry->trigger = 0;
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entry->mask = 0;
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entry->dest = cfg->dest_apicid;
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uv_write_global_mmr64(info->pnode, info->offset, mmr_value);
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}
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static void uv_noop(struct irq_data *data) { }
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static int
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uv_set_irq_affinity(struct irq_data *data, const struct cpumask *mask,
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bool force)
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{
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struct irq_data *parent = data->parent_data;
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struct irq_cfg *cfg = irqd_cfg(data);
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int ret;
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ret = parent->chip->irq_set_affinity(parent, mask, force);
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if (ret >= 0) {
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uv_program_mmr(cfg, data->chip_data);
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send_cleanup_vector(cfg);
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}
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return ret;
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}
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static struct irq_chip uv_irq_chip = {
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.name = "UV-CORE",
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.irq_mask = uv_noop,
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.irq_unmask = uv_noop,
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.irq_eoi = apic_ack_irq,
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.irq_set_affinity = uv_set_irq_affinity,
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};
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static int uv_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct uv_irq_2_mmr_pnode *chip_data;
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struct irq_alloc_info *info = arg;
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struct irq_data *irq_data = irq_domain_get_irq_data(domain, virq);
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int ret;
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if (nr_irqs > 1 || !info || info->type != X86_IRQ_ALLOC_TYPE_UV)
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return -EINVAL;
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chip_data = kmalloc_node(sizeof(*chip_data), GFP_KERNEL,
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irq_data_get_node(irq_data));
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if (!chip_data)
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return -ENOMEM;
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ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
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if (ret >= 0) {
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if (info->uv_limit == UV_AFFINITY_CPU)
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irq_set_status_flags(virq, IRQ_NO_BALANCING);
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else
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irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
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chip_data->pnode = uv_blade_to_pnode(info->uv_blade);
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chip_data->offset = info->uv_offset;
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irq_domain_set_info(domain, virq, virq, &uv_irq_chip, chip_data,
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handle_percpu_irq, NULL, info->uv_name);
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} else {
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kfree(chip_data);
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}
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return ret;
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}
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static void uv_domain_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs)
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{
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struct irq_data *irq_data = irq_domain_get_irq_data(domain, virq);
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BUG_ON(nr_irqs != 1);
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kfree(irq_data->chip_data);
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irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
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irq_clear_status_flags(virq, IRQ_NO_BALANCING);
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irq_domain_free_irqs_top(domain, virq, nr_irqs);
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}
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/*
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* Re-target the irq to the specified CPU and enable the specified MMR located
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* on the specified blade to allow the sending of MSIs to the specified CPU.
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*/
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static int uv_domain_activate(struct irq_domain *domain,
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struct irq_data *irq_data, bool reserve)
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{
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uv_program_mmr(irqd_cfg(irq_data), irq_data->chip_data);
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return 0;
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}
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/*
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* Disable the specified MMR located on the specified blade so that MSIs are
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* longer allowed to be sent.
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*/
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static void uv_domain_deactivate(struct irq_domain *domain,
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struct irq_data *irq_data)
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{
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unsigned long mmr_value;
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struct uv_IO_APIC_route_entry *entry;
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mmr_value = 0;
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entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
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entry->mask = 1;
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uv_program_mmr(irqd_cfg(irq_data), irq_data->chip_data);
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}
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static const struct irq_domain_ops uv_domain_ops = {
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.alloc = uv_domain_alloc,
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.free = uv_domain_free,
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.activate = uv_domain_activate,
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.deactivate = uv_domain_deactivate,
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};
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static struct irq_domain *uv_get_irq_domain(void)
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{
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static struct irq_domain *uv_domain;
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static DEFINE_MUTEX(uv_lock);
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struct fwnode_handle *fn;
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mutex_lock(&uv_lock);
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if (uv_domain)
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goto out;
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fn = irq_domain_alloc_named_fwnode("UV-CORE");
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if (!fn)
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goto out;
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uv_domain = irq_domain_create_tree(fn, &uv_domain_ops, NULL);
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if (uv_domain)
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uv_domain->parent = x86_vector_domain;
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else
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irq_domain_free_fwnode(fn);
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out:
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mutex_unlock(&uv_lock);
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return uv_domain;
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}
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/*
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* Set up a mapping of an available irq and vector, and enable the specified
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* MMR that defines the MSI that is to be sent to the specified CPU when an
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* interrupt is raised.
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*/
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int uv_setup_irq(char *irq_name, int cpu, int mmr_blade,
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unsigned long mmr_offset, int limit)
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{
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struct irq_alloc_info info;
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struct irq_domain *domain = uv_get_irq_domain();
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if (!domain)
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return -ENOMEM;
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init_irq_alloc_info(&info, cpumask_of(cpu));
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info.type = X86_IRQ_ALLOC_TYPE_UV;
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info.uv_limit = limit;
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info.uv_blade = mmr_blade;
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info.uv_offset = mmr_offset;
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info.uv_name = irq_name;
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return irq_domain_alloc_irqs(domain, 1,
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uv_blade_to_memory_nid(mmr_blade), &info);
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}
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EXPORT_SYMBOL_GPL(uv_setup_irq);
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/*
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* Tear down a mapping of an irq and vector, and disable the specified MMR that
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* defined the MSI that was to be sent to the specified CPU when an interrupt
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* was raised.
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*
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* Set mmr_blade and mmr_offset to what was passed in on uv_setup_irq().
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*/
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void uv_teardown_irq(unsigned int irq)
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{
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irq_domain_free_irqs(irq, 1);
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}
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EXPORT_SYMBOL_GPL(uv_teardown_irq);
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