/*
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* Intel MID Power Management Unit (PWRMU) device driver
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*
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* Copyright (C) 2016, Intel Corporation
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*
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* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* Intel MID Power Management Unit device driver handles the South Complex PCI
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* devices such as GPDMA, SPI, I2C, PWM, and so on. By default PCI core
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* modifies bits in PMCSR register in the PCI configuration space. This is not
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* enough on some SoCs like Intel Tangier. In such case PCI core sets a new
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* power state of the device in question through a PM hook registered in struct
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* pci_platform_pm_ops (see drivers/pci/pci-mid.c).
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <asm/intel-mid.h>
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/* Registers */
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#define PM_STS 0x00
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#define PM_CMD 0x04
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#define PM_ICS 0x08
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#define PM_WKC(x) (0x10 + (x) * 4)
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#define PM_WKS(x) (0x18 + (x) * 4)
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#define PM_SSC(x) (0x20 + (x) * 4)
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#define PM_SSS(x) (0x30 + (x) * 4)
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/* Bits in PM_STS */
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#define PM_STS_BUSY (1 << 8)
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/* Bits in PM_CMD */
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#define PM_CMD_CMD(x) ((x) << 0)
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#define PM_CMD_IOC (1 << 8)
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#define PM_CMD_CM_NOP (0 << 9)
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#define PM_CMD_CM_IMMEDIATE (1 << 9)
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#define PM_CMD_CM_DELAY (2 << 9)
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#define PM_CMD_CM_TRIGGER (3 << 9)
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/* System states */
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#define PM_CMD_SYS_STATE_S5 (5 << 16)
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/* Trigger variants */
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#define PM_CMD_CFG_TRIGGER_NC (3 << 19)
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/* Message to wait for TRIGGER_NC case */
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#define TRIGGER_NC_MSG_2 (2 << 22)
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/* List of commands */
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#define CMD_SET_CFG 0x01
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/* Bits in PM_ICS */
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#define PM_ICS_INT_STATUS(x) ((x) & 0xff)
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#define PM_ICS_IE (1 << 8)
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#define PM_ICS_IP (1 << 9)
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#define PM_ICS_SW_INT_STS (1 << 10)
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/* List of interrupts */
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#define INT_INVALID 0
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#define INT_CMD_COMPLETE 1
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#define INT_CMD_ERR 2
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#define INT_WAKE_EVENT 3
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#define INT_LSS_POWER_ERR 4
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#define INT_S0iX_MSG_ERR 5
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#define INT_NO_C6 6
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#define INT_TRIGGER_ERR 7
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#define INT_INACTIVITY 8
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/* South Complex devices */
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#define LSS_MAX_SHARED_DEVS 4
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#define LSS_MAX_DEVS 64
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#define LSS_WS_BITS 1 /* wake state width */
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#define LSS_PWS_BITS 2 /* power state width */
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/* Supported device IDs */
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#define PCI_DEVICE_ID_PENWELL 0x0828
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#define PCI_DEVICE_ID_TANGIER 0x11a1
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struct mid_pwr_dev {
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struct pci_dev *pdev;
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pci_power_t state;
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};
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struct mid_pwr {
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struct device *dev;
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void __iomem *regs;
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int irq;
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bool available;
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struct mutex lock;
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struct mid_pwr_dev lss[LSS_MAX_DEVS][LSS_MAX_SHARED_DEVS];
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};
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static struct mid_pwr *midpwr;
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static u32 mid_pwr_get_state(struct mid_pwr *pwr, int reg)
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{
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return readl(pwr->regs + PM_SSS(reg));
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}
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static void mid_pwr_set_state(struct mid_pwr *pwr, int reg, u32 value)
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{
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writel(value, pwr->regs + PM_SSC(reg));
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}
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static void mid_pwr_set_wake(struct mid_pwr *pwr, int reg, u32 value)
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{
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writel(value, pwr->regs + PM_WKC(reg));
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}
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static void mid_pwr_interrupt_disable(struct mid_pwr *pwr)
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{
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writel(~PM_ICS_IE, pwr->regs + PM_ICS);
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}
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static bool mid_pwr_is_busy(struct mid_pwr *pwr)
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{
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return !!(readl(pwr->regs + PM_STS) & PM_STS_BUSY);
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}
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/* Wait 500ms that the latest PWRMU command finished */
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static int mid_pwr_wait(struct mid_pwr *pwr)
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{
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unsigned int count = 500000;
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bool busy;
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do {
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busy = mid_pwr_is_busy(pwr);
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if (!busy)
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return 0;
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udelay(1);
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} while (--count);
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return -EBUSY;
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}
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static int mid_pwr_wait_for_cmd(struct mid_pwr *pwr, u8 cmd)
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{
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writel(PM_CMD_CMD(cmd) | PM_CMD_CM_IMMEDIATE, pwr->regs + PM_CMD);
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return mid_pwr_wait(pwr);
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}
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static int __update_power_state(struct mid_pwr *pwr, int reg, int bit, int new)
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{
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int curstate;
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u32 power;
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int ret;
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/* Check if the device is already in desired state */
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power = mid_pwr_get_state(pwr, reg);
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curstate = (power >> bit) & 3;
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if (curstate == new)
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return 0;
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/* Update the power state */
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mid_pwr_set_state(pwr, reg, (power & ~(3 << bit)) | (new << bit));
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/* Send command to SCU */
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ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);
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if (ret)
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return ret;
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/* Check if the device is already in desired state */
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power = mid_pwr_get_state(pwr, reg);
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curstate = (power >> bit) & 3;
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if (curstate != new)
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return -EAGAIN;
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return 0;
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}
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static pci_power_t __find_weakest_power_state(struct mid_pwr_dev *lss,
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struct pci_dev *pdev,
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pci_power_t state)
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{
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pci_power_t weakest = PCI_D3hot;
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unsigned int j;
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/* Find device in cache or first free cell */
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for (j = 0; j < LSS_MAX_SHARED_DEVS; j++) {
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if (lss[j].pdev == pdev || !lss[j].pdev)
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break;
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}
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/* Store the desired state in cache */
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if (j < LSS_MAX_SHARED_DEVS) {
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lss[j].pdev = pdev;
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lss[j].state = state;
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} else {
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dev_WARN(&pdev->dev, "No room for device in PWRMU LSS cache\n");
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weakest = state;
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}
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/* Find the power state we may use */
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for (j = 0; j < LSS_MAX_SHARED_DEVS; j++) {
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if (lss[j].state < weakest)
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weakest = lss[j].state;
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}
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return weakest;
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}
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static int __set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev,
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pci_power_t state, int id, int reg, int bit)
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{
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const char *name;
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int ret;
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state = __find_weakest_power_state(pwr->lss[id], pdev, state);
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name = pci_power_name(state);
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ret = __update_power_state(pwr, reg, bit, (__force int)state);
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if (ret) {
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dev_warn(&pdev->dev, "Can't set power state %s: %d\n", name, ret);
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return ret;
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}
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dev_vdbg(&pdev->dev, "Set power state %s\n", name);
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return 0;
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}
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static int mid_pwr_set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev,
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pci_power_t state)
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{
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int id, reg, bit;
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int ret;
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id = intel_mid_pwr_get_lss_id(pdev);
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if (id < 0)
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return id;
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reg = (id * LSS_PWS_BITS) / 32;
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bit = (id * LSS_PWS_BITS) % 32;
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/* We support states between PCI_D0 and PCI_D3hot */
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if (state < PCI_D0)
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state = PCI_D0;
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if (state > PCI_D3hot)
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state = PCI_D3hot;
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mutex_lock(&pwr->lock);
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ret = __set_power_state(pwr, pdev, state, id, reg, bit);
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mutex_unlock(&pwr->lock);
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return ret;
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}
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int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
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{
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struct mid_pwr *pwr = midpwr;
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int ret = 0;
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might_sleep();
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if (pwr && pwr->available)
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ret = mid_pwr_set_power_state(pwr, pdev, state);
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dev_vdbg(&pdev->dev, "set_power_state() returns %d\n", ret);
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return 0;
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}
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pci_power_t intel_mid_pci_get_power_state(struct pci_dev *pdev)
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{
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struct mid_pwr *pwr = midpwr;
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int id, reg, bit;
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u32 power;
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if (!pwr || !pwr->available)
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return PCI_UNKNOWN;
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id = intel_mid_pwr_get_lss_id(pdev);
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if (id < 0)
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return PCI_UNKNOWN;
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reg = (id * LSS_PWS_BITS) / 32;
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bit = (id * LSS_PWS_BITS) % 32;
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power = mid_pwr_get_state(pwr, reg);
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return (__force pci_power_t)((power >> bit) & 3);
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}
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void intel_mid_pwr_power_off(void)
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{
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struct mid_pwr *pwr = midpwr;
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u32 cmd = PM_CMD_SYS_STATE_S5 |
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PM_CMD_CMD(CMD_SET_CFG) |
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PM_CMD_CM_TRIGGER |
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PM_CMD_CFG_TRIGGER_NC |
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TRIGGER_NC_MSG_2;
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/* Send command to SCU */
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writel(cmd, pwr->regs + PM_CMD);
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mid_pwr_wait(pwr);
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}
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int intel_mid_pwr_get_lss_id(struct pci_dev *pdev)
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{
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int vndr;
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u8 id;
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/*
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* Mapping to PWRMU index is kept in the Logical SubSystem ID byte of
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* Vendor capability.
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*/
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vndr = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
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if (!vndr)
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return -EINVAL;
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/* Read the Logical SubSystem ID byte */
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pci_read_config_byte(pdev, vndr + INTEL_MID_PWR_LSS_OFFSET, &id);
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if (!(id & INTEL_MID_PWR_LSS_TYPE))
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return -ENODEV;
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id &= ~INTEL_MID_PWR_LSS_TYPE;
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if (id >= LSS_MAX_DEVS)
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return -ERANGE;
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return id;
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}
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static irqreturn_t mid_pwr_irq_handler(int irq, void *dev_id)
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{
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struct mid_pwr *pwr = dev_id;
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u32 ics;
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ics = readl(pwr->regs + PM_ICS);
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if (!(ics & PM_ICS_IP))
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return IRQ_NONE;
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writel(ics | PM_ICS_IP, pwr->regs + PM_ICS);
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dev_warn(pwr->dev, "Unexpected IRQ: %#x\n", PM_ICS_INT_STATUS(ics));
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return IRQ_HANDLED;
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}
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struct mid_pwr_device_info {
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int (*set_initial_state)(struct mid_pwr *pwr);
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};
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static int mid_pwr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct mid_pwr_device_info *info = (void *)id->driver_data;
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struct device *dev = &pdev->dev;
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struct mid_pwr *pwr;
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int ret;
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ret = pcim_enable_device(pdev);
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if (ret < 0) {
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dev_err(&pdev->dev, "error: could not enable device\n");
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return ret;
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}
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ret = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
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if (ret) {
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dev_err(&pdev->dev, "I/O memory remapping failed\n");
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return ret;
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}
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pwr = devm_kzalloc(dev, sizeof(*pwr), GFP_KERNEL);
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if (!pwr)
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return -ENOMEM;
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pwr->dev = dev;
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pwr->regs = pcim_iomap_table(pdev)[0];
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pwr->irq = pdev->irq;
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mutex_init(&pwr->lock);
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/* Disable interrupts */
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mid_pwr_interrupt_disable(pwr);
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if (info && info->set_initial_state) {
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ret = info->set_initial_state(pwr);
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if (ret)
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dev_warn(dev, "Can't set initial state: %d\n", ret);
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}
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ret = devm_request_irq(dev, pdev->irq, mid_pwr_irq_handler,
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IRQF_NO_SUSPEND, pci_name(pdev), pwr);
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if (ret)
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return ret;
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pwr->available = true;
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midpwr = pwr;
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pci_set_drvdata(pdev, pwr);
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return 0;
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}
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static int mid_set_initial_state(struct mid_pwr *pwr, const u32 *states)
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{
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unsigned int i, j;
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int ret;
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/*
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* Enable wake events.
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*
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* PWRMU supports up to 32 sources for wake up the system. Ungate them
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* all here.
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*/
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mid_pwr_set_wake(pwr, 0, 0xffffffff);
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mid_pwr_set_wake(pwr, 1, 0xffffffff);
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/*
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* Power off South Complex devices.
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*
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* There is a map (see a note below) of 64 devices with 2 bits per each
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* on 32-bit HW registers. The following calls set all devices to one
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* known initial state, i.e. PCI_D3hot. This is done in conjunction
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* with PMCSR setting in arch/x86/pci/intel_mid_pci.c.
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*
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* NOTE: The actual device mapping is provided by a platform at run
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* time using vendor capability of PCI configuration space.
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*/
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mid_pwr_set_state(pwr, 0, states[0]);
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mid_pwr_set_state(pwr, 1, states[1]);
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mid_pwr_set_state(pwr, 2, states[2]);
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mid_pwr_set_state(pwr, 3, states[3]);
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/* Send command to SCU */
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ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);
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if (ret)
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return ret;
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for (i = 0; i < LSS_MAX_DEVS; i++) {
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for (j = 0; j < LSS_MAX_SHARED_DEVS; j++)
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pwr->lss[i][j].state = PCI_D3hot;
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}
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return 0;
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}
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static int pnw_set_initial_state(struct mid_pwr *pwr)
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{
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/* On Penwell SRAM must stay powered on */
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static const u32 states[] = {
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0xf00fffff, /* PM_SSC(0) */
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0xffffffff, /* PM_SSC(1) */
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0xffffffff, /* PM_SSC(2) */
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0xffffffff, /* PM_SSC(3) */
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};
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return mid_set_initial_state(pwr, states);
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}
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static int tng_set_initial_state(struct mid_pwr *pwr)
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{
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static const u32 states[] = {
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0xffffffff, /* PM_SSC(0) */
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0xffffffff, /* PM_SSC(1) */
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0xffffffff, /* PM_SSC(2) */
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0xffffffff, /* PM_SSC(3) */
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};
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return mid_set_initial_state(pwr, states);
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}
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static const struct mid_pwr_device_info pnw_info = {
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.set_initial_state = pnw_set_initial_state,
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};
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static const struct mid_pwr_device_info tng_info = {
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.set_initial_state = tng_set_initial_state,
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};
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/* This table should be in sync with the one in drivers/pci/pci-mid.c */
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static const struct pci_device_id mid_pwr_pci_ids[] = {
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&pnw_info },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&tng_info },
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{}
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};
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static struct pci_driver mid_pwr_pci_driver = {
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.name = "intel_mid_pwr",
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.probe = mid_pwr_probe,
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.id_table = mid_pwr_pci_ids,
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};
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builtin_pci_driver(mid_pwr_pci_driver);
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