/* SPDX-License-Identifier: GPL-2.0 */
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/*---------------------------------------------------------------------------+
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| control_w.h |
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| Copyright (C) 1992,1993 |
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| W. Metzenthen, 22 Parker St, Ormond, Vic 3163, |
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| Australia. E-mail billm@vaxc.cc.monash.edu.au |
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+---------------------------------------------------------------------------*/
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#ifndef _CONTROLW_H_
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#define _CONTROLW_H_
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#ifdef __ASSEMBLY__
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#define _Const_(x) $##x
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#else
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#define _Const_(x) x
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#endif
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#define CW_RC _Const_(0x0C00) /* rounding control */
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#define CW_PC _Const_(0x0300) /* precision control */
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#define CW_Precision Const_(0x0020) /* loss of precision mask */
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#define CW_Underflow Const_(0x0010) /* underflow mask */
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#define CW_Overflow Const_(0x0008) /* overflow mask */
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#define CW_ZeroDiv Const_(0x0004) /* divide by zero mask */
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#define CW_Denormal Const_(0x0002) /* denormalized operand mask */
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#define CW_Invalid Const_(0x0001) /* invalid operation mask */
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#define CW_Exceptions _Const_(0x003f) /* all masks */
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#define RC_RND _Const_(0x0000)
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#define RC_DOWN _Const_(0x0400)
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#define RC_UP _Const_(0x0800)
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#define RC_CHOP _Const_(0x0C00)
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/* p 15-5: Precision control bits affect only the following:
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ADD, SUB(R), MUL, DIV(R), and SQRT */
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#define PR_24_BITS _Const_(0x000)
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#define PR_53_BITS _Const_(0x200)
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#define PR_64_BITS _Const_(0x300)
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#define PR_RESERVED_BITS _Const_(0x100)
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/* FULL_PRECISION simulates all exceptions masked */
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#define FULL_PRECISION (PR_64_BITS | RC_RND | 0x3f)
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#endif /* _CONTROLW_H_ */
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