/*
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* Performance events x86 architecture header
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*
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* Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
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* Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
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* Copyright (C) 2009 Jaswinder Singh Rajput
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* Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
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* Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
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* Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
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* Copyright (C) 2009 Google, Inc., Stephane Eranian
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*
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* For licencing details see kernel-base/COPYING
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*/
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#include <linux/perf_event.h>
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#include <asm/intel_ds.h>
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/* To enable MSR tracing please use the generic trace points. */
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/*
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* | NHM/WSM | SNB |
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* register -------------------------------
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* | HT | no HT | HT | no HT |
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*-----------------------------------------
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* offcore | core | core | cpu | core |
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* lbr_sel | core | core | cpu | core |
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* ld_lat | cpu | core | cpu | core |
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*-----------------------------------------
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*
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* Given that there is a small number of shared regs,
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* we can pre-allocate their slot in the per-cpu
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* per-core reg tables.
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*/
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enum extra_reg_type {
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EXTRA_REG_NONE = -1, /* not used */
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EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
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EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
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EXTRA_REG_LBR = 2, /* lbr_select */
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EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */
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EXTRA_REG_FE = 4, /* fe_* */
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EXTRA_REG_MAX /* number of entries needed */
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};
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struct event_constraint {
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union {
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unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
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u64 idxmsk64;
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};
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u64 code;
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u64 cmask;
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int weight;
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int overlap;
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int flags;
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};
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/*
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* struct hw_perf_event.flags flags
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*/
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#define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */
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#define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */
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#define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */
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#define PERF_X86_EVENT_COMMITTED 0x0008 /* event passed commit_txn */
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#define PERF_X86_EVENT_PEBS_LD_HSW 0x0010 /* haswell style datala, load */
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#define PERF_X86_EVENT_PEBS_NA_HSW 0x0020 /* haswell style datala, unknown */
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#define PERF_X86_EVENT_EXCL 0x0040 /* HT exclusivity on counter */
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#define PERF_X86_EVENT_DYNAMIC 0x0080 /* dynamic alloc'd constraint */
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#define PERF_X86_EVENT_RDPMC_ALLOWED 0x0100 /* grant rdpmc permission */
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#define PERF_X86_EVENT_EXCL_ACCT 0x0200 /* accounted EXCL event */
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#define PERF_X86_EVENT_AUTO_RELOAD 0x0400 /* use PEBS auto-reload */
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#define PERF_X86_EVENT_LARGE_PEBS 0x0800 /* use large PEBS */
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struct amd_nb {
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int nb_id; /* NorthBridge id */
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int refcnt; /* reference count */
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struct perf_event *owners[X86_PMC_IDX_MAX];
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struct event_constraint event_constraints[X86_PMC_IDX_MAX];
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};
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#define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1)
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/*
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* Flags PEBS can handle without an PMI.
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*
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* TID can only be handled by flushing at context switch.
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* REGS_USER can be handled for events limited to ring 3.
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*
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*/
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#define LARGE_PEBS_FLAGS \
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(PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
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PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
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PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
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PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
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PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \
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PERF_SAMPLE_PERIOD)
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#define PEBS_GP_REGS \
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((1ULL << PERF_REG_X86_AX) | \
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(1ULL << PERF_REG_X86_BX) | \
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(1ULL << PERF_REG_X86_CX) | \
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(1ULL << PERF_REG_X86_DX) | \
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(1ULL << PERF_REG_X86_DI) | \
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(1ULL << PERF_REG_X86_SI) | \
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(1ULL << PERF_REG_X86_SP) | \
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(1ULL << PERF_REG_X86_BP) | \
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(1ULL << PERF_REG_X86_IP) | \
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(1ULL << PERF_REG_X86_FLAGS) | \
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(1ULL << PERF_REG_X86_R8) | \
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(1ULL << PERF_REG_X86_R9) | \
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(1ULL << PERF_REG_X86_R10) | \
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(1ULL << PERF_REG_X86_R11) | \
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(1ULL << PERF_REG_X86_R12) | \
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(1ULL << PERF_REG_X86_R13) | \
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(1ULL << PERF_REG_X86_R14) | \
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(1ULL << PERF_REG_X86_R15))
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/*
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* Per register state.
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*/
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struct er_account {
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raw_spinlock_t lock; /* per-core: protect structure */
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u64 config; /* extra MSR config */
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u64 reg; /* extra MSR number */
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atomic_t ref; /* reference count */
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};
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/*
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* Per core/cpu state
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*
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* Used to coordinate shared registers between HT threads or
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* among events on a single PMU.
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*/
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struct intel_shared_regs {
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struct er_account regs[EXTRA_REG_MAX];
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int refcnt; /* per-core: #HT threads */
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unsigned core_id; /* per-core: core id */
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};
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enum intel_excl_state_type {
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INTEL_EXCL_UNUSED = 0, /* counter is unused */
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INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */
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INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */
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};
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struct intel_excl_states {
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enum intel_excl_state_type state[X86_PMC_IDX_MAX];
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bool sched_started; /* true if scheduling has started */
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};
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struct intel_excl_cntrs {
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raw_spinlock_t lock;
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struct intel_excl_states states[2];
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union {
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u16 has_exclusive[2];
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u32 exclusive_present;
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};
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int refcnt; /* per-core: #HT threads */
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unsigned core_id; /* per-core: core id */
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};
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struct x86_perf_task_context;
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#define MAX_LBR_ENTRIES 32
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enum {
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X86_PERF_KFREE_SHARED = 0,
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X86_PERF_KFREE_EXCL = 1,
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X86_PERF_KFREE_MAX
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};
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struct cpu_hw_events {
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/*
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* Generic x86 PMC bits
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*/
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struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
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unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
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unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
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int enabled;
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int n_events; /* the # of events in the below arrays */
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int n_added; /* the # last events in the below arrays;
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they've never been enabled yet */
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int n_txn; /* the # last events in the below arrays;
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added in the current transaction */
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int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
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u64 tags[X86_PMC_IDX_MAX];
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struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
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struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
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int n_excl; /* the number of exclusive events */
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unsigned int txn_flags;
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int is_fake;
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/*
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* Intel DebugStore bits
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*/
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struct debug_store *ds;
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void *ds_pebs_vaddr;
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void *ds_bts_vaddr;
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u64 pebs_enabled;
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int n_pebs;
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int n_large_pebs;
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/*
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* Intel LBR bits
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*/
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int lbr_users;
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struct perf_branch_stack lbr_stack;
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struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
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struct er_account *lbr_sel;
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u64 br_sel;
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struct x86_perf_task_context *last_task_ctx;
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int last_log_id;
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/*
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* Intel host/guest exclude bits
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*/
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u64 intel_ctrl_guest_mask;
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u64 intel_ctrl_host_mask;
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struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
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/*
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* Intel checkpoint mask
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*/
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u64 intel_cp_status;
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/*
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* manage shared (per-core, per-cpu) registers
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* used on Intel NHM/WSM/SNB
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*/
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struct intel_shared_regs *shared_regs;
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/*
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* manage exclusive counter access between hyperthread
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*/
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struct event_constraint *constraint_list; /* in enable order */
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struct intel_excl_cntrs *excl_cntrs;
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int excl_thread_id; /* 0 or 1 */
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/*
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* SKL TSX_FORCE_ABORT shadow
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*/
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u64 tfa_shadow;
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/*
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* AMD specific bits
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*/
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struct amd_nb *amd_nb;
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/* Inverted mask of bits to clear in the perf_ctr ctrl registers */
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u64 perf_ctr_virt_mask;
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void *kfree_on_online[X86_PERF_KFREE_MAX];
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};
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#define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\
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{ .idxmsk64 = (n) }, \
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.code = (c), \
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.cmask = (m), \
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.weight = (w), \
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.overlap = (o), \
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.flags = f, \
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}
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#define EVENT_CONSTRAINT(c, n, m) \
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__EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
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#define INTEL_EXCLEVT_CONSTRAINT(c, n) \
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__EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\
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0, PERF_X86_EVENT_EXCL)
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/*
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* The overlap flag marks event constraints with overlapping counter
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* masks. This is the case if the counter mask of such an event is not
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* a subset of any other counter mask of a constraint with an equal or
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* higher weight, e.g.:
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*
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* c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
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* c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
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* c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
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*
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* The event scheduler may not select the correct counter in the first
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* cycle because it needs to know which subsequent events will be
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* scheduled. It may fail to schedule the events then. So we set the
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* overlap flag for such constraints to give the scheduler a hint which
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* events to select for counter rescheduling.
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*
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* Care must be taken as the rescheduling algorithm is O(n!) which
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* will increase scheduling cycles for an over-committed system
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* dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
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* and its counter masks must be kept at a minimum.
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*/
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#define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
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__EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
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/*
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* Constraint on the Event code.
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*/
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#define INTEL_EVENT_CONSTRAINT(c, n) \
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EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
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/*
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* Constraint on the Event code + UMask + fixed-mask
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*
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* filter mask to validate fixed counter events.
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* the following filters disqualify for fixed counters:
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* - inv
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* - edge
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* - cnt-mask
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* - in_tx
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* - in_tx_checkpointed
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* The other filters are supported by fixed counters.
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* The any-thread option is supported starting with v3.
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*/
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#define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
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#define FIXED_EVENT_CONSTRAINT(c, n) \
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EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
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/*
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* Constraint on the Event code + UMask
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*/
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#define INTEL_UEVENT_CONSTRAINT(c, n) \
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EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
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/* Constraint on specific umask bit only + event */
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#define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \
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EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c))
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/* Like UEVENT_CONSTRAINT, but match flags too */
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#define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \
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EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
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#define INTEL_EXCLUEVT_CONSTRAINT(c, n) \
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__EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
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HWEIGHT(n), 0, PERF_X86_EVENT_EXCL)
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#define INTEL_PLD_CONSTRAINT(c, n) \
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__EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
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HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
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#define INTEL_PST_CONSTRAINT(c, n) \
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__EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
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HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
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/* Event constraint, but match on all event flags too. */
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#define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
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EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
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/* Check only flags, but allow all event/umask */
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#define INTEL_ALL_EVENT_CONSTRAINT(code, n) \
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EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
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/* Check flags and event code, and set the HSW store flag */
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#define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \
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__EVENT_CONSTRAINT(code, n, \
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ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
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HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
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/* Check flags and event code, and set the HSW load flag */
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#define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \
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__EVENT_CONSTRAINT(code, n, \
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ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
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HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
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#define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \
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__EVENT_CONSTRAINT(code, n, \
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ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
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HWEIGHT(n), 0, \
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PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
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/* Check flags and event code/umask, and set the HSW store flag */
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#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
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__EVENT_CONSTRAINT(code, n, \
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INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
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HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
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#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \
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__EVENT_CONSTRAINT(code, n, \
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INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
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HWEIGHT(n), 0, \
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PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL)
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/* Check flags and event code/umask, and set the HSW load flag */
|
#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
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__EVENT_CONSTRAINT(code, n, \
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INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
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HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
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#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \
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__EVENT_CONSTRAINT(code, n, \
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INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
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HWEIGHT(n), 0, \
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PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
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|
/* Check flags and event code/umask, and set the HSW N/A flag */
|
#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
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__EVENT_CONSTRAINT(code, n, \
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INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
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HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW)
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|
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/*
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* We define the end marker as having a weight of -1
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* to enable blacklisting of events using a counter bitmask
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* of zero and thus a weight of zero.
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* The end marker has a weight that cannot possibly be
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* obtained from counting the bits in the bitmask.
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*/
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#define EVENT_CONSTRAINT_END { .weight = -1 }
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/*
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* Check for end marker with weight == -1
|
*/
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#define for_each_event_constraint(e, c) \
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for ((e) = (c); (e)->weight != -1; (e)++)
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|
/*
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* Extra registers for specific events.
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*
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* Some events need large masks and require external MSRs.
|
* Those extra MSRs end up being shared for all events on
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* a PMU and sometimes between PMU of sibling HT threads.
|
* In either case, the kernel needs to handle conflicting
|
* accesses to those extra, shared, regs. The data structure
|
* to manage those registers is stored in cpu_hw_event.
|
*/
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struct extra_reg {
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unsigned int event;
|
unsigned int msr;
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u64 config_mask;
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u64 valid_mask;
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int idx; /* per_xxx->regs[] reg index */
|
bool extra_msr_access;
|
};
|
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#define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
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.event = (e), \
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.msr = (ms), \
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.config_mask = (m), \
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.valid_mask = (vm), \
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.idx = EXTRA_REG_##i, \
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.extra_msr_access = true, \
|
}
|
|
#define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
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EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
|
|
#define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
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EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
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ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
|
|
#define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
|
INTEL_UEVENT_EXTRA_REG(c, \
|
MSR_PEBS_LD_LAT_THRESHOLD, \
|
0xffff, \
|
LDLAT)
|
|
#define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
|
|
union perf_capabilities {
|
struct {
|
u64 lbr_format:6;
|
u64 pebs_trap:1;
|
u64 pebs_arch_reg:1;
|
u64 pebs_format:4;
|
u64 smm_freeze:1;
|
/*
|
* PMU supports separate counter range for writing
|
* values > 32bit.
|
*/
|
u64 full_width_write:1;
|
};
|
u64 capabilities;
|
};
|
|
struct x86_pmu_quirk {
|
struct x86_pmu_quirk *next;
|
void (*func)(void);
|
};
|
|
union x86_pmu_config {
|
struct {
|
u64 event:8,
|
umask:8,
|
usr:1,
|
os:1,
|
edge:1,
|
pc:1,
|
interrupt:1,
|
__reserved1:1,
|
en:1,
|
inv:1,
|
cmask:8,
|
event2:4,
|
__reserved2:4,
|
go:1,
|
ho:1;
|
} bits;
|
u64 value;
|
};
|
|
#define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
|
|
enum {
|
x86_lbr_exclusive_lbr,
|
x86_lbr_exclusive_bts,
|
x86_lbr_exclusive_pt,
|
x86_lbr_exclusive_max,
|
};
|
|
/*
|
* struct x86_pmu - generic x86 pmu
|
*/
|
struct x86_pmu {
|
/*
|
* Generic x86 PMC bits
|
*/
|
const char *name;
|
int version;
|
int (*handle_irq)(struct pt_regs *);
|
void (*disable_all)(void);
|
void (*enable_all)(int added);
|
void (*enable)(struct perf_event *);
|
void (*disable)(struct perf_event *);
|
void (*add)(struct perf_event *);
|
void (*del)(struct perf_event *);
|
void (*read)(struct perf_event *event);
|
int (*hw_config)(struct perf_event *event);
|
int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
|
unsigned eventsel;
|
unsigned perfctr;
|
int (*addr_offset)(int index, bool eventsel);
|
int (*rdpmc_index)(int index);
|
u64 (*event_map)(int);
|
int max_events;
|
int num_counters;
|
int num_counters_fixed;
|
int cntval_bits;
|
u64 cntval_mask;
|
union {
|
unsigned long events_maskl;
|
unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
|
};
|
int events_mask_len;
|
int apic;
|
u64 max_period;
|
struct event_constraint *
|
(*get_event_constraints)(struct cpu_hw_events *cpuc,
|
int idx,
|
struct perf_event *event);
|
|
void (*put_event_constraints)(struct cpu_hw_events *cpuc,
|
struct perf_event *event);
|
|
void (*start_scheduling)(struct cpu_hw_events *cpuc);
|
|
void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr);
|
|
void (*stop_scheduling)(struct cpu_hw_events *cpuc);
|
|
struct event_constraint *event_constraints;
|
struct x86_pmu_quirk *quirks;
|
int perfctr_second_write;
|
bool late_ack;
|
u64 (*limit_period)(struct perf_event *event, u64 l);
|
|
/*
|
* sysfs attrs
|
*/
|
int attr_rdpmc_broken;
|
int attr_rdpmc;
|
struct attribute **format_attrs;
|
struct attribute **event_attrs;
|
struct attribute **caps_attrs;
|
|
ssize_t (*events_sysfs_show)(char *page, u64 config);
|
struct attribute **cpu_events;
|
|
unsigned long attr_freeze_on_smi;
|
struct attribute **attrs;
|
|
/*
|
* CPU Hotplug hooks
|
*/
|
int (*cpu_prepare)(int cpu);
|
void (*cpu_starting)(int cpu);
|
void (*cpu_dying)(int cpu);
|
void (*cpu_dead)(int cpu);
|
|
void (*check_microcode)(void);
|
void (*sched_task)(struct perf_event_context *ctx,
|
bool sched_in);
|
|
/*
|
* Intel Arch Perfmon v2+
|
*/
|
u64 intel_ctrl;
|
union perf_capabilities intel_cap;
|
|
/*
|
* Intel DebugStore bits
|
*/
|
unsigned int bts :1,
|
bts_active :1,
|
pebs :1,
|
pebs_active :1,
|
pebs_broken :1,
|
pebs_prec_dist :1,
|
pebs_no_tlb :1;
|
int pebs_record_size;
|
int pebs_buffer_size;
|
void (*drain_pebs)(struct pt_regs *regs);
|
struct event_constraint *pebs_constraints;
|
void (*pebs_aliases)(struct perf_event *event);
|
int max_pebs_events;
|
unsigned long large_pebs_flags;
|
|
/*
|
* Intel LBR
|
*/
|
unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
|
int lbr_nr; /* hardware stack size */
|
u64 lbr_sel_mask; /* LBR_SELECT valid bits */
|
const int *lbr_sel_map; /* lbr_select mappings */
|
bool lbr_double_abort; /* duplicated lbr aborts */
|
bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
|
|
/*
|
* Intel PT/LBR/BTS are exclusive
|
*/
|
atomic_t lbr_exclusive[x86_lbr_exclusive_max];
|
|
/*
|
* AMD bits
|
*/
|
unsigned int amd_nb_constraints : 1;
|
|
/*
|
* Extra registers for events
|
*/
|
struct extra_reg *extra_regs;
|
unsigned int flags;
|
|
/*
|
* Intel host/guest support (KVM)
|
*/
|
struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
|
|
/*
|
* Check period value for PERF_EVENT_IOC_PERIOD ioctl.
|
*/
|
int (*check_period) (struct perf_event *event, u64 period);
|
};
|
|
struct x86_perf_task_context {
|
u64 lbr_from[MAX_LBR_ENTRIES];
|
u64 lbr_to[MAX_LBR_ENTRIES];
|
u64 lbr_info[MAX_LBR_ENTRIES];
|
int tos;
|
int valid_lbrs;
|
int lbr_callstack_users;
|
int lbr_stack_state;
|
int log_id;
|
};
|
|
#define x86_add_quirk(func_) \
|
do { \
|
static struct x86_pmu_quirk __quirk __initdata = { \
|
.func = func_, \
|
}; \
|
__quirk.next = x86_pmu.quirks; \
|
x86_pmu.quirks = &__quirk; \
|
} while (0)
|
|
/*
|
* x86_pmu flags
|
*/
|
#define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */
|
#define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */
|
#define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */
|
#define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */
|
#define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */
|
#define PMU_FL_TFA 0x20 /* deal with TSX force abort */
|
|
#define EVENT_VAR(_id) event_attr_##_id
|
#define EVENT_PTR(_id) &event_attr_##_id.attr.attr
|
|
#define EVENT_ATTR(_name, _id) \
|
static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
|
.attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
|
.id = PERF_COUNT_HW_##_id, \
|
.event_str = NULL, \
|
};
|
|
#define EVENT_ATTR_STR(_name, v, str) \
|
static struct perf_pmu_events_attr event_attr_##v = { \
|
.attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
|
.id = 0, \
|
.event_str = str, \
|
};
|
|
#define EVENT_ATTR_STR_HT(_name, v, noht, ht) \
|
static struct perf_pmu_events_ht_attr event_attr_##v = { \
|
.attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\
|
.id = 0, \
|
.event_str_noht = noht, \
|
.event_str_ht = ht, \
|
}
|
|
extern struct x86_pmu x86_pmu __read_mostly;
|
|
static inline bool x86_pmu_has_lbr_callstack(void)
|
{
|
return x86_pmu.lbr_sel_map &&
|
x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0;
|
}
|
|
DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
|
|
int x86_perf_event_set_period(struct perf_event *event);
|
|
/*
|
* Generalized hw caching related hw_event table, filled
|
* in on a per model basis. A value of 0 means
|
* 'not supported', -1 means 'hw_event makes no sense on
|
* this CPU', any other value means the raw hw_event
|
* ID.
|
*/
|
|
#define C(x) PERF_COUNT_HW_CACHE_##x
|
|
extern u64 __read_mostly hw_cache_event_ids
|
[PERF_COUNT_HW_CACHE_MAX]
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
[PERF_COUNT_HW_CACHE_RESULT_MAX];
|
extern u64 __read_mostly hw_cache_extra_regs
|
[PERF_COUNT_HW_CACHE_MAX]
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
[PERF_COUNT_HW_CACHE_RESULT_MAX];
|
|
u64 x86_perf_event_update(struct perf_event *event);
|
|
static inline unsigned int x86_pmu_config_addr(int index)
|
{
|
return x86_pmu.eventsel + (x86_pmu.addr_offset ?
|
x86_pmu.addr_offset(index, true) : index);
|
}
|
|
static inline unsigned int x86_pmu_event_addr(int index)
|
{
|
return x86_pmu.perfctr + (x86_pmu.addr_offset ?
|
x86_pmu.addr_offset(index, false) : index);
|
}
|
|
static inline int x86_pmu_rdpmc_index(int index)
|
{
|
return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
|
}
|
|
int x86_add_exclusive(unsigned int what);
|
|
void x86_del_exclusive(unsigned int what);
|
|
int x86_reserve_hardware(void);
|
|
void x86_release_hardware(void);
|
|
int x86_pmu_max_precise(void);
|
|
void hw_perf_lbr_event_destroy(struct perf_event *event);
|
|
int x86_setup_perfctr(struct perf_event *event);
|
|
int x86_pmu_hw_config(struct perf_event *event);
|
|
void x86_pmu_disable_all(void);
|
|
static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
|
u64 enable_mask)
|
{
|
u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
|
|
if (hwc->extra_reg.reg)
|
wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
|
wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
|
}
|
|
void x86_pmu_enable_all(int added);
|
|
int perf_assign_events(struct event_constraint **constraints, int n,
|
int wmin, int wmax, int gpmax, int *assign);
|
int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
|
|
void x86_pmu_stop(struct perf_event *event, int flags);
|
|
static inline void x86_pmu_disable_event(struct perf_event *event)
|
{
|
u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
|
struct hw_perf_event *hwc = &event->hw;
|
|
wrmsrl(hwc->config_base, hwc->config & ~disable_mask);
|
}
|
|
void x86_pmu_enable_event(struct perf_event *event);
|
|
int x86_pmu_handle_irq(struct pt_regs *regs);
|
|
extern struct event_constraint emptyconstraint;
|
|
extern struct event_constraint unconstrained;
|
|
static inline bool kernel_ip(unsigned long ip)
|
{
|
#ifdef CONFIG_X86_32
|
return ip > PAGE_OFFSET;
|
#else
|
return (long)ip < 0;
|
#endif
|
}
|
|
/*
|
* Not all PMUs provide the right context information to place the reported IP
|
* into full context. Specifically segment registers are typically not
|
* supplied.
|
*
|
* Assuming the address is a linear address (it is for IBS), we fake the CS and
|
* vm86 mode using the known zero-based code segment and 'fix up' the registers
|
* to reflect this.
|
*
|
* Intel PEBS/LBR appear to typically provide the effective address, nothing
|
* much we can do about that but pray and treat it like a linear address.
|
*/
|
static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
|
{
|
regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
|
if (regs->flags & X86_VM_MASK)
|
regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
|
regs->ip = ip;
|
}
|
|
ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
|
ssize_t intel_event_sysfs_show(char *page, u64 config);
|
|
struct attribute **merge_attr(struct attribute **a, struct attribute **b);
|
|
ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
|
char *page);
|
ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
|
char *page);
|
|
#ifdef CONFIG_CPU_SUP_AMD
|
|
int amd_pmu_init(void);
|
|
#else /* CONFIG_CPU_SUP_AMD */
|
|
static inline int amd_pmu_init(void)
|
{
|
return 0;
|
}
|
|
#endif /* CONFIG_CPU_SUP_AMD */
|
|
#ifdef CONFIG_CPU_SUP_INTEL
|
|
static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period)
|
{
|
struct hw_perf_event *hwc = &event->hw;
|
unsigned int hw_event, bts_event;
|
|
if (event->attr.freq)
|
return false;
|
|
hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
|
bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
|
|
return hw_event == bts_event && period == 1;
|
}
|
|
static inline bool intel_pmu_has_bts(struct perf_event *event)
|
{
|
struct hw_perf_event *hwc = &event->hw;
|
|
return intel_pmu_has_bts_period(event, hwc->sample_period);
|
}
|
|
int intel_pmu_save_and_restart(struct perf_event *event);
|
|
struct event_constraint *
|
x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
|
struct perf_event *event);
|
|
extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu);
|
extern void intel_cpuc_finish(struct cpu_hw_events *cpuc);
|
|
int intel_pmu_init(void);
|
|
void init_debug_store_on_cpu(int cpu);
|
|
void fini_debug_store_on_cpu(int cpu);
|
|
void release_ds_buffers(void);
|
|
void reserve_ds_buffers(void);
|
|
extern struct event_constraint bts_constraint;
|
|
void intel_pmu_enable_bts(u64 config);
|
|
void intel_pmu_disable_bts(void);
|
|
int intel_pmu_drain_bts_buffer(void);
|
|
extern struct event_constraint intel_core2_pebs_event_constraints[];
|
|
extern struct event_constraint intel_atom_pebs_event_constraints[];
|
|
extern struct event_constraint intel_slm_pebs_event_constraints[];
|
|
extern struct event_constraint intel_glm_pebs_event_constraints[];
|
|
extern struct event_constraint intel_glp_pebs_event_constraints[];
|
|
extern struct event_constraint intel_nehalem_pebs_event_constraints[];
|
|
extern struct event_constraint intel_westmere_pebs_event_constraints[];
|
|
extern struct event_constraint intel_snb_pebs_event_constraints[];
|
|
extern struct event_constraint intel_ivb_pebs_event_constraints[];
|
|
extern struct event_constraint intel_hsw_pebs_event_constraints[];
|
|
extern struct event_constraint intel_bdw_pebs_event_constraints[];
|
|
extern struct event_constraint intel_skl_pebs_event_constraints[];
|
|
struct event_constraint *intel_pebs_constraints(struct perf_event *event);
|
|
void intel_pmu_pebs_add(struct perf_event *event);
|
|
void intel_pmu_pebs_del(struct perf_event *event);
|
|
void intel_pmu_pebs_enable(struct perf_event *event);
|
|
void intel_pmu_pebs_disable(struct perf_event *event);
|
|
void intel_pmu_pebs_enable_all(void);
|
|
void intel_pmu_pebs_disable_all(void);
|
|
void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in);
|
|
void intel_pmu_auto_reload_read(struct perf_event *event);
|
|
void intel_ds_init(void);
|
|
void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in);
|
|
u64 lbr_from_signext_quirk_wr(u64 val);
|
|
void intel_pmu_lbr_reset(void);
|
|
void intel_pmu_lbr_add(struct perf_event *event);
|
|
void intel_pmu_lbr_del(struct perf_event *event);
|
|
void intel_pmu_lbr_enable_all(bool pmi);
|
|
void intel_pmu_lbr_disable_all(void);
|
|
void intel_pmu_lbr_read(void);
|
|
void intel_pmu_lbr_init_core(void);
|
|
void intel_pmu_lbr_init_nhm(void);
|
|
void intel_pmu_lbr_init_atom(void);
|
|
void intel_pmu_lbr_init_slm(void);
|
|
void intel_pmu_lbr_init_snb(void);
|
|
void intel_pmu_lbr_init_hsw(void);
|
|
void intel_pmu_lbr_init_skl(void);
|
|
void intel_pmu_lbr_init_knl(void);
|
|
void intel_pmu_pebs_data_source_nhm(void);
|
|
void intel_pmu_pebs_data_source_skl(bool pmem);
|
|
int intel_pmu_setup_lbr_filter(struct perf_event *event);
|
|
void intel_pt_interrupt(void);
|
|
int intel_bts_interrupt(void);
|
|
void intel_bts_enable_local(void);
|
|
void intel_bts_disable_local(void);
|
|
int p4_pmu_init(void);
|
|
int p6_pmu_init(void);
|
|
int knc_pmu_init(void);
|
|
static inline int is_ht_workaround_enabled(void)
|
{
|
return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED);
|
}
|
|
#else /* CONFIG_CPU_SUP_INTEL */
|
|
static inline void reserve_ds_buffers(void)
|
{
|
}
|
|
static inline void release_ds_buffers(void)
|
{
|
}
|
|
static inline int intel_pmu_init(void)
|
{
|
return 0;
|
}
|
|
static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
|
{
|
return 0;
|
}
|
|
static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc)
|
{
|
}
|
|
static inline int is_ht_workaround_enabled(void)
|
{
|
return 0;
|
}
|
#endif /* CONFIG_CPU_SUP_INTEL */
|
