// SPDX-License-Identifier: GPL-2.0
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#include <linux/perf_event.h>
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#include <linux/nospec.h>
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#include <asm/intel-family.h>
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enum perf_msr_id {
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PERF_MSR_TSC = 0,
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PERF_MSR_APERF = 1,
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PERF_MSR_MPERF = 2,
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PERF_MSR_PPERF = 3,
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PERF_MSR_SMI = 4,
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PERF_MSR_PTSC = 5,
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PERF_MSR_IRPERF = 6,
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PERF_MSR_THERM = 7,
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PERF_MSR_THERM_SNAP = 8,
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PERF_MSR_THERM_UNIT = 9,
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PERF_MSR_EVENT_MAX,
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};
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static bool test_aperfmperf(int idx)
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{
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return boot_cpu_has(X86_FEATURE_APERFMPERF);
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}
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static bool test_ptsc(int idx)
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{
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return boot_cpu_has(X86_FEATURE_PTSC);
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}
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static bool test_irperf(int idx)
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{
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return boot_cpu_has(X86_FEATURE_IRPERF);
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}
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static bool test_therm_status(int idx)
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{
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return boot_cpu_has(X86_FEATURE_DTHERM);
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}
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static bool test_intel(int idx)
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{
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if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
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boot_cpu_data.x86 != 6)
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return false;
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switch (boot_cpu_data.x86_model) {
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case INTEL_FAM6_NEHALEM:
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case INTEL_FAM6_NEHALEM_G:
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case INTEL_FAM6_NEHALEM_EP:
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case INTEL_FAM6_NEHALEM_EX:
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case INTEL_FAM6_WESTMERE:
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case INTEL_FAM6_WESTMERE_EP:
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case INTEL_FAM6_WESTMERE_EX:
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case INTEL_FAM6_SANDYBRIDGE:
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case INTEL_FAM6_SANDYBRIDGE_X:
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case INTEL_FAM6_IVYBRIDGE:
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case INTEL_FAM6_IVYBRIDGE_X:
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case INTEL_FAM6_HASWELL_CORE:
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case INTEL_FAM6_HASWELL_X:
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case INTEL_FAM6_HASWELL_ULT:
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case INTEL_FAM6_HASWELL_GT3E:
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case INTEL_FAM6_BROADWELL_CORE:
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case INTEL_FAM6_BROADWELL_XEON_D:
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case INTEL_FAM6_BROADWELL_GT3E:
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case INTEL_FAM6_BROADWELL_X:
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case INTEL_FAM6_ATOM_SILVERMONT:
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case INTEL_FAM6_ATOM_SILVERMONT_X:
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case INTEL_FAM6_ATOM_AIRMONT:
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case INTEL_FAM6_ATOM_GOLDMONT:
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case INTEL_FAM6_ATOM_GOLDMONT_X:
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case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
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case INTEL_FAM6_XEON_PHI_KNL:
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case INTEL_FAM6_XEON_PHI_KNM:
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if (idx == PERF_MSR_SMI)
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return true;
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break;
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case INTEL_FAM6_SKYLAKE_MOBILE:
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case INTEL_FAM6_SKYLAKE_DESKTOP:
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case INTEL_FAM6_SKYLAKE_X:
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case INTEL_FAM6_KABYLAKE_MOBILE:
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case INTEL_FAM6_KABYLAKE_DESKTOP:
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case INTEL_FAM6_ICELAKE_MOBILE:
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if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
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return true;
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break;
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}
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return false;
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}
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struct perf_msr {
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u64 msr;
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struct perf_pmu_events_attr *attr;
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bool (*test)(int idx);
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};
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PMU_EVENT_ATTR_STRING(tsc, evattr_tsc, "event=0x00" );
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PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01" );
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PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02" );
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PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03" );
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PMU_EVENT_ATTR_STRING(smi, evattr_smi, "event=0x04" );
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PMU_EVENT_ATTR_STRING(ptsc, evattr_ptsc, "event=0x05" );
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PMU_EVENT_ATTR_STRING(irperf, evattr_irperf, "event=0x06" );
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PMU_EVENT_ATTR_STRING(cpu_thermal_margin, evattr_therm, "event=0x07" );
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PMU_EVENT_ATTR_STRING(cpu_thermal_margin.snapshot, evattr_therm_snap, "1" );
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PMU_EVENT_ATTR_STRING(cpu_thermal_margin.unit, evattr_therm_unit, "C" );
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static struct perf_msr msr[] = {
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[PERF_MSR_TSC] = { 0, &evattr_tsc, NULL, },
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[PERF_MSR_APERF] = { MSR_IA32_APERF, &evattr_aperf, test_aperfmperf, },
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[PERF_MSR_MPERF] = { MSR_IA32_MPERF, &evattr_mperf, test_aperfmperf, },
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[PERF_MSR_PPERF] = { MSR_PPERF, &evattr_pperf, test_intel, },
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[PERF_MSR_SMI] = { MSR_SMI_COUNT, &evattr_smi, test_intel, },
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[PERF_MSR_PTSC] = { MSR_F15H_PTSC, &evattr_ptsc, test_ptsc, },
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[PERF_MSR_IRPERF] = { MSR_F17H_IRPERF, &evattr_irperf, test_irperf, },
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[PERF_MSR_THERM] = { MSR_IA32_THERM_STATUS, &evattr_therm, test_therm_status, },
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[PERF_MSR_THERM_SNAP] = { MSR_IA32_THERM_STATUS, &evattr_therm_snap, test_therm_status, },
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[PERF_MSR_THERM_UNIT] = { MSR_IA32_THERM_STATUS, &evattr_therm_unit, test_therm_status, },
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};
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static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {
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NULL,
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};
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static struct attribute_group events_attr_group = {
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.name = "events",
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.attrs = events_attrs,
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};
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PMU_FORMAT_ATTR(event, "config:0-63");
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static struct attribute *format_attrs[] = {
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&format_attr_event.attr,
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NULL,
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};
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static struct attribute_group format_attr_group = {
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.name = "format",
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.attrs = format_attrs,
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};
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static const struct attribute_group *attr_groups[] = {
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&events_attr_group,
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&format_attr_group,
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NULL,
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};
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static int msr_event_init(struct perf_event *event)
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{
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u64 cfg = event->attr.config;
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if (event->attr.type != event->pmu->type)
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return -ENOENT;
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/* unsupported modes and filters */
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if (event->attr.exclude_user ||
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event->attr.exclude_kernel ||
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event->attr.exclude_hv ||
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event->attr.exclude_idle ||
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event->attr.exclude_host ||
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event->attr.exclude_guest ||
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event->attr.sample_period) /* no sampling */
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return -EINVAL;
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if (cfg >= PERF_MSR_EVENT_MAX)
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return -EINVAL;
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cfg = array_index_nospec((unsigned long)cfg, PERF_MSR_EVENT_MAX);
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if (!msr[cfg].attr)
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return -EINVAL;
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event->hw.idx = -1;
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event->hw.event_base = msr[cfg].msr;
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event->hw.config = cfg;
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return 0;
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}
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static inline u64 msr_read_counter(struct perf_event *event)
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{
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u64 now;
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if (event->hw.event_base)
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rdmsrl(event->hw.event_base, now);
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else
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now = rdtsc_ordered();
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return now;
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}
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static void msr_event_update(struct perf_event *event)
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{
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u64 prev, now;
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s64 delta;
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/* Careful, an NMI might modify the previous event value: */
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again:
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prev = local64_read(&event->hw.prev_count);
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now = msr_read_counter(event);
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if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev)
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goto again;
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delta = now - prev;
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if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) {
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delta = sign_extend64(delta, 31);
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local64_add(delta, &event->count);
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} else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) {
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/* If valid, extract digital readout, otherwise set to -1: */
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now = now & (1ULL << 31) ? (now >> 16) & 0x3f : -1;
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local64_set(&event->count, now);
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} else {
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local64_add(delta, &event->count);
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}
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}
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static void msr_event_start(struct perf_event *event, int flags)
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{
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u64 now = msr_read_counter(event);
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local64_set(&event->hw.prev_count, now);
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}
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static void msr_event_stop(struct perf_event *event, int flags)
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{
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msr_event_update(event);
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}
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static void msr_event_del(struct perf_event *event, int flags)
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{
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msr_event_stop(event, PERF_EF_UPDATE);
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}
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static int msr_event_add(struct perf_event *event, int flags)
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{
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if (flags & PERF_EF_START)
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msr_event_start(event, flags);
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return 0;
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}
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static struct pmu pmu_msr = {
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.task_ctx_nr = perf_sw_context,
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.attr_groups = attr_groups,
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.event_init = msr_event_init,
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.add = msr_event_add,
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.del = msr_event_del,
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.start = msr_event_start,
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.stop = msr_event_stop,
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.read = msr_event_update,
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.capabilities = PERF_PMU_CAP_NO_INTERRUPT,
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};
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static int __init msr_init(void)
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{
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int i, j = 0;
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if (!boot_cpu_has(X86_FEATURE_TSC)) {
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pr_cont("no MSR PMU driver.\n");
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return 0;
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}
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/* Probe the MSRs. */
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for (i = PERF_MSR_TSC + 1; i < PERF_MSR_EVENT_MAX; i++) {
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u64 val;
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/* Virt sucks; you cannot tell if a R/O MSR is present :/ */
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if (!msr[i].test(i) || rdmsrl_safe(msr[i].msr, &val))
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msr[i].attr = NULL;
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}
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/* List remaining MSRs in the sysfs attrs. */
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for (i = 0; i < PERF_MSR_EVENT_MAX; i++) {
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if (msr[i].attr)
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events_attrs[j++] = &msr[i].attr->attr.attr;
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}
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events_attrs[j] = NULL;
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perf_pmu_register(&pmu_msr, "msr", -1);
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return 0;
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}
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device_initcall(msr_init);
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