/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <asm/apicdef.h>
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#include <linux/perf_event.h>
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#include "../perf_event.h"
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#define UNCORE_PMU_NAME_LEN 32
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#define UNCORE_PMU_HRTIMER_INTERVAL (60LL * NSEC_PER_SEC)
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#define UNCORE_SNB_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC)
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#define UNCORE_FIXED_EVENT 0xff
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#define UNCORE_PMC_IDX_MAX_GENERIC 8
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#define UNCORE_PMC_IDX_MAX_FIXED 1
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#define UNCORE_PMC_IDX_MAX_FREERUNNING 1
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#define UNCORE_PMC_IDX_FIXED UNCORE_PMC_IDX_MAX_GENERIC
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#define UNCORE_PMC_IDX_FREERUNNING (UNCORE_PMC_IDX_FIXED + \
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UNCORE_PMC_IDX_MAX_FIXED)
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#define UNCORE_PMC_IDX_MAX (UNCORE_PMC_IDX_FREERUNNING + \
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UNCORE_PMC_IDX_MAX_FREERUNNING)
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#define UNCORE_PCI_DEV_FULL_DATA(dev, func, type, idx) \
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((dev << 24) | (func << 16) | (type << 8) | idx)
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#define UNCORE_PCI_DEV_DATA(type, idx) ((type << 8) | idx)
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#define UNCORE_PCI_DEV_DEV(data) ((data >> 24) & 0xff)
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#define UNCORE_PCI_DEV_FUNC(data) ((data >> 16) & 0xff)
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#define UNCORE_PCI_DEV_TYPE(data) ((data >> 8) & 0xff)
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#define UNCORE_PCI_DEV_IDX(data) (data & 0xff)
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#define UNCORE_EXTRA_PCI_DEV 0xff
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#define UNCORE_EXTRA_PCI_DEV_MAX 4
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#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)
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struct pci_extra_dev {
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struct pci_dev *dev[UNCORE_EXTRA_PCI_DEV_MAX];
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};
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struct intel_uncore_ops;
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struct intel_uncore_pmu;
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struct intel_uncore_box;
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struct uncore_event_desc;
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struct freerunning_counters;
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struct intel_uncore_type {
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const char *name;
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int num_counters;
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int num_boxes;
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int perf_ctr_bits;
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int fixed_ctr_bits;
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int num_freerunning_types;
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unsigned perf_ctr;
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unsigned event_ctl;
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unsigned event_mask;
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unsigned event_mask_ext;
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unsigned fixed_ctr;
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unsigned fixed_ctl;
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unsigned box_ctl;
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unsigned msr_offset;
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unsigned num_shared_regs:8;
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unsigned single_fixed:1;
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unsigned pair_ctr_ctl:1;
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unsigned *msr_offsets;
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struct event_constraint unconstrainted;
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struct event_constraint *constraints;
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struct intel_uncore_pmu *pmus;
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struct intel_uncore_ops *ops;
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struct uncore_event_desc *event_descs;
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struct freerunning_counters *freerunning;
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const struct attribute_group *attr_groups[4];
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struct pmu *pmu; /* for custom pmu ops */
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};
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#define pmu_group attr_groups[0]
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#define format_group attr_groups[1]
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#define events_group attr_groups[2]
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struct intel_uncore_ops {
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void (*init_box)(struct intel_uncore_box *);
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void (*exit_box)(struct intel_uncore_box *);
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void (*disable_box)(struct intel_uncore_box *);
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void (*enable_box)(struct intel_uncore_box *);
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void (*disable_event)(struct intel_uncore_box *, struct perf_event *);
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void (*enable_event)(struct intel_uncore_box *, struct perf_event *);
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u64 (*read_counter)(struct intel_uncore_box *, struct perf_event *);
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int (*hw_config)(struct intel_uncore_box *, struct perf_event *);
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struct event_constraint *(*get_constraint)(struct intel_uncore_box *,
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struct perf_event *);
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void (*put_constraint)(struct intel_uncore_box *, struct perf_event *);
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};
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struct intel_uncore_pmu {
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struct pmu pmu;
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char name[UNCORE_PMU_NAME_LEN];
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int pmu_idx;
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int func_id;
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bool registered;
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atomic_t activeboxes;
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struct intel_uncore_type *type;
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struct intel_uncore_box **boxes;
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};
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struct intel_uncore_extra_reg {
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raw_spinlock_t lock;
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u64 config, config1, config2;
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atomic_t ref;
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};
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struct intel_uncore_box {
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int pci_phys_id;
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int pkgid; /* Logical package ID */
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int n_active; /* number of active events */
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int n_events;
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int cpu; /* cpu to collect events */
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unsigned long flags;
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atomic_t refcnt;
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struct perf_event *events[UNCORE_PMC_IDX_MAX];
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struct perf_event *event_list[UNCORE_PMC_IDX_MAX];
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struct event_constraint *event_constraint[UNCORE_PMC_IDX_MAX];
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unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
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u64 tags[UNCORE_PMC_IDX_MAX];
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struct pci_dev *pci_dev;
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struct intel_uncore_pmu *pmu;
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u64 hrtimer_duration; /* hrtimer timeout for this box */
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struct hrtimer hrtimer;
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struct list_head list;
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struct list_head active_list;
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void *io_addr;
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struct intel_uncore_extra_reg shared_regs[0];
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};
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#define UNCORE_BOX_FLAG_INITIATED 0
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#define UNCORE_BOX_FLAG_CTL_OFFS8 1 /* event config registers are 8-byte apart */
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struct uncore_event_desc {
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struct device_attribute attr;
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const char *config;
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};
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struct freerunning_counters {
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unsigned int counter_base;
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unsigned int counter_offset;
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unsigned int box_offset;
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unsigned int num_counters;
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unsigned int bits;
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};
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struct pci2phy_map {
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struct list_head list;
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int segment;
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int pbus_to_physid[256];
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};
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struct pci2phy_map *__find_pci2phy_map(int segment);
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ssize_t uncore_event_show(struct device *dev,
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struct device_attribute *attr, char *buf);
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#define INTEL_UNCORE_EVENT_DESC(_name, _config) \
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{ \
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.attr = __ATTR(_name, 0444, uncore_event_show, NULL), \
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.config = _config, \
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}
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#define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format) \
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static ssize_t __uncore_##_var##_show(struct device *dev, \
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struct device_attribute *attr, \
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char *page) \
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{ \
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BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
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return sprintf(page, _format "\n"); \
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} \
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static struct device_attribute format_attr_##_var = \
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__ATTR(_name, 0444, __uncore_##_var##_show, NULL)
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static inline bool uncore_pmc_fixed(int idx)
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{
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return idx == UNCORE_PMC_IDX_FIXED;
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}
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static inline bool uncore_pmc_freerunning(int idx)
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{
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return idx == UNCORE_PMC_IDX_FREERUNNING;
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}
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static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box)
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{
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return box->pmu->type->box_ctl;
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}
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static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box)
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{
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return box->pmu->type->fixed_ctl;
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}
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static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
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{
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return box->pmu->type->fixed_ctr;
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}
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static inline
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unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
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{
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if (test_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags))
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return idx * 8 + box->pmu->type->event_ctl;
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return idx * 4 + box->pmu->type->event_ctl;
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}
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static inline
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unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
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{
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return idx * 8 + box->pmu->type->perf_ctr;
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}
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static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
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{
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struct intel_uncore_pmu *pmu = box->pmu;
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return pmu->type->msr_offsets ?
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pmu->type->msr_offsets[pmu->pmu_idx] :
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pmu->type->msr_offset * pmu->pmu_idx;
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}
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static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
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{
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if (!box->pmu->type->box_ctl)
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return 0;
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return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
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}
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static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
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{
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if (!box->pmu->type->fixed_ctl)
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return 0;
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return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
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}
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static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
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{
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return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
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}
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/*
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* In the uncore document, there is no event-code assigned to free running
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* counters. Some events need to be defined to indicate the free running
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* counters. The events are encoded as event-code + umask-code.
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*
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* The event-code for all free running counters is 0xff, which is the same as
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* the fixed counters.
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*
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* The umask-code is used to distinguish a fixed counter and a free running
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* counter, and different types of free running counters.
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* - For fixed counters, the umask-code is 0x0X.
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* X indicates the index of the fixed counter, which starts from 0.
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* - For free running counters, the umask-code uses the rest of the space.
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* It would bare the format of 0xXY.
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* X stands for the type of free running counters, which starts from 1.
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* Y stands for the index of free running counters of same type, which
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* starts from 0.
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*
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* For example, there are three types of IIO free running counters on Skylake
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* server, IO CLOCKS counters, BANDWIDTH counters and UTILIZATION counters.
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* The event-code for all the free running counters is 0xff.
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* 'ioclk' is the first counter of IO CLOCKS. IO CLOCKS is the first type,
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* which umask-code starts from 0x10.
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* So 'ioclk' is encoded as event=0xff,umask=0x10
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* 'bw_in_port2' is the third counter of BANDWIDTH counters. BANDWIDTH is
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* the second type, which umask-code starts from 0x20.
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* So 'bw_in_port2' is encoded as event=0xff,umask=0x22
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*/
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static inline unsigned int uncore_freerunning_idx(u64 config)
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{
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return ((config >> 8) & 0xf);
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}
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#define UNCORE_FREERUNNING_UMASK_START 0x10
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static inline unsigned int uncore_freerunning_type(u64 config)
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{
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return ((((config >> 8) - UNCORE_FREERUNNING_UMASK_START) >> 4) & 0xf);
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}
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static inline
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unsigned int uncore_freerunning_counter(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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unsigned int type = uncore_freerunning_type(event->hw.config);
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unsigned int idx = uncore_freerunning_idx(event->hw.config);
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struct intel_uncore_pmu *pmu = box->pmu;
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return pmu->type->freerunning[type].counter_base +
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pmu->type->freerunning[type].counter_offset * idx +
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pmu->type->freerunning[type].box_offset * pmu->pmu_idx;
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}
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static inline
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unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
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{
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return box->pmu->type->event_ctl +
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(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
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uncore_msr_box_offset(box);
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}
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static inline
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unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
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{
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return box->pmu->type->perf_ctr +
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(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
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uncore_msr_box_offset(box);
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}
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static inline
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unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
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{
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if (box->pci_dev)
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return uncore_pci_fixed_ctl(box);
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else
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return uncore_msr_fixed_ctl(box);
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}
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static inline
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unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
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{
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if (box->pci_dev)
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return uncore_pci_fixed_ctr(box);
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else
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return uncore_msr_fixed_ctr(box);
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}
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static inline
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unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx)
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{
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if (box->pci_dev)
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return uncore_pci_event_ctl(box, idx);
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else
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return uncore_msr_event_ctl(box, idx);
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}
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static inline
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unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx)
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{
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if (box->pci_dev)
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return uncore_pci_perf_ctr(box, idx);
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else
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return uncore_msr_perf_ctr(box, idx);
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}
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static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box)
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{
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return box->pmu->type->perf_ctr_bits;
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}
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static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
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{
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return box->pmu->type->fixed_ctr_bits;
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}
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static inline
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unsigned int uncore_freerunning_bits(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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unsigned int type = uncore_freerunning_type(event->hw.config);
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return box->pmu->type->freerunning[type].bits;
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}
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static inline int uncore_num_freerunning(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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unsigned int type = uncore_freerunning_type(event->hw.config);
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return box->pmu->type->freerunning[type].num_counters;
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}
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static inline int uncore_num_freerunning_types(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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return box->pmu->type->num_freerunning_types;
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}
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static inline bool check_valid_freerunning_event(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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unsigned int type = uncore_freerunning_type(event->hw.config);
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unsigned int idx = uncore_freerunning_idx(event->hw.config);
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return (type < uncore_num_freerunning_types(box, event)) &&
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(idx < uncore_num_freerunning(box, event));
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}
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static inline int uncore_num_counters(struct intel_uncore_box *box)
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{
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return box->pmu->type->num_counters;
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}
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static inline bool is_freerunning_event(struct perf_event *event)
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{
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u64 cfg = event->attr.config;
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return ((cfg & UNCORE_FIXED_EVENT) == UNCORE_FIXED_EVENT) &&
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(((cfg >> 8) & 0xff) >= UNCORE_FREERUNNING_UMASK_START);
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}
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/* Check and reject invalid config */
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static inline int uncore_freerunning_hw_config(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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if (is_freerunning_event(event))
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return 0;
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return -EINVAL;
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}
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static inline void uncore_disable_event(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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box->pmu->type->ops->disable_event(box, event);
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}
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static inline void uncore_enable_event(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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box->pmu->type->ops->enable_event(box, event);
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}
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static inline u64 uncore_read_counter(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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return box->pmu->type->ops->read_counter(box, event);
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}
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static inline void uncore_box_init(struct intel_uncore_box *box)
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{
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if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
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if (box->pmu->type->ops->init_box)
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box->pmu->type->ops->init_box(box);
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}
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}
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static inline void uncore_box_exit(struct intel_uncore_box *box)
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{
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if (test_and_clear_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
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if (box->pmu->type->ops->exit_box)
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box->pmu->type->ops->exit_box(box);
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}
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}
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static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
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{
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return (box->pkgid < 0);
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}
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static inline struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
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{
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return container_of(event->pmu, struct intel_uncore_pmu, pmu);
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}
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static inline struct intel_uncore_box *uncore_event_to_box(struct perf_event *event)
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{
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return event->pmu_private;
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}
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struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu);
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u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event);
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void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
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void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
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void uncore_pmu_event_start(struct perf_event *event, int flags);
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void uncore_pmu_event_stop(struct perf_event *event, int flags);
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int uncore_pmu_event_add(struct perf_event *event, int flags);
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void uncore_pmu_event_del(struct perf_event *event, int flags);
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void uncore_pmu_event_read(struct perf_event *event);
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void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event);
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struct event_constraint *
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uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event);
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void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event);
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u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx);
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extern struct intel_uncore_type **uncore_msr_uncores;
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extern struct intel_uncore_type **uncore_pci_uncores;
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extern struct pci_driver *uncore_pci_driver;
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extern raw_spinlock_t pci2phy_map_lock;
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extern struct list_head pci2phy_map_head;
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extern struct pci_extra_dev *uncore_extra_pci_dev;
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extern struct event_constraint uncore_constraint_empty;
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/* uncore_snb.c */
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int snb_uncore_pci_init(void);
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int ivb_uncore_pci_init(void);
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int hsw_uncore_pci_init(void);
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int bdw_uncore_pci_init(void);
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int skl_uncore_pci_init(void);
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void snb_uncore_cpu_init(void);
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void nhm_uncore_cpu_init(void);
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void skl_uncore_cpu_init(void);
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int snb_pci2phy_map_init(int devid);
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/* uncore_snbep.c */
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int snbep_uncore_pci_init(void);
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void snbep_uncore_cpu_init(void);
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int ivbep_uncore_pci_init(void);
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void ivbep_uncore_cpu_init(void);
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int hswep_uncore_pci_init(void);
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void hswep_uncore_cpu_init(void);
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int bdx_uncore_pci_init(void);
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void bdx_uncore_cpu_init(void);
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int knl_uncore_pci_init(void);
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void knl_uncore_cpu_init(void);
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int skx_uncore_pci_init(void);
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void skx_uncore_cpu_init(void);
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/* uncore_nhmex.c */
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void nhmex_uncore_cpu_init(void);
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