/*
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* Performance events - AMD Processor Power Reporting Mechanism
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*
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* Copyright (C) 2016 Advanced Micro Devices, Inc.
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*
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* Author: Huang Rui <ray.huang@amd.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/perf_event.h>
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#include <asm/cpu_device_id.h>
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#include "../perf_event.h"
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#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
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#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
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#define MSR_F15H_PTSC 0xc0010280
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/* Event code: LSB 8 bits, passed in attr->config any other bit is reserved. */
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#define AMD_POWER_EVENT_MASK 0xFFULL
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/*
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* Accumulated power status counters.
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*/
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#define AMD_POWER_EVENTSEL_PKG 1
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/*
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* The ratio of compute unit power accumulator sample period to the
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* PTSC period.
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*/
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static unsigned int cpu_pwr_sample_ratio;
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/* Maximum accumulated power of a compute unit. */
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static u64 max_cu_acc_power;
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static struct pmu pmu_class;
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/*
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* Accumulated power represents the sum of each compute unit's (CU) power
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* consumption. On any core of each CU we read the total accumulated power from
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* MSR_F15H_CU_PWR_ACCUMULATOR. cpu_mask represents CPU bit map of all cores
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* which are picked to measure the power for the CUs they belong to.
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*/
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static cpumask_t cpu_mask;
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static void event_update(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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u64 prev_pwr_acc, new_pwr_acc, prev_ptsc, new_ptsc;
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u64 delta, tdelta;
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prev_pwr_acc = hwc->pwr_acc;
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prev_ptsc = hwc->ptsc;
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rdmsrl(MSR_F15H_CU_PWR_ACCUMULATOR, new_pwr_acc);
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rdmsrl(MSR_F15H_PTSC, new_ptsc);
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/*
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* Calculate the CU power consumption over a time period, the unit of
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* final value (delta) is micro-Watts. Then add it to the event count.
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*/
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if (new_pwr_acc < prev_pwr_acc) {
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delta = max_cu_acc_power + new_pwr_acc;
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delta -= prev_pwr_acc;
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} else
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delta = new_pwr_acc - prev_pwr_acc;
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delta *= cpu_pwr_sample_ratio * 1000;
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tdelta = new_ptsc - prev_ptsc;
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do_div(delta, tdelta);
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local64_add(delta, &event->count);
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}
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static void __pmu_event_start(struct perf_event *event)
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{
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if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
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return;
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event->hw.state = 0;
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rdmsrl(MSR_F15H_PTSC, event->hw.ptsc);
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rdmsrl(MSR_F15H_CU_PWR_ACCUMULATOR, event->hw.pwr_acc);
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}
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static void pmu_event_start(struct perf_event *event, int mode)
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{
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__pmu_event_start(event);
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}
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static void pmu_event_stop(struct perf_event *event, int mode)
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{
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struct hw_perf_event *hwc = &event->hw;
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/* Mark event as deactivated and stopped. */
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if (!(hwc->state & PERF_HES_STOPPED))
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hwc->state |= PERF_HES_STOPPED;
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/* Check if software counter update is necessary. */
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if ((mode & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
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/*
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* Drain the remaining delta count out of an event
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* that we are disabling:
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*/
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event_update(event);
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hwc->state |= PERF_HES_UPTODATE;
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}
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}
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static int pmu_event_add(struct perf_event *event, int mode)
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{
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struct hw_perf_event *hwc = &event->hw;
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hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
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if (mode & PERF_EF_START)
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__pmu_event_start(event);
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return 0;
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}
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static void pmu_event_del(struct perf_event *event, int flags)
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{
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pmu_event_stop(event, PERF_EF_UPDATE);
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}
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static int pmu_event_init(struct perf_event *event)
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{
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u64 cfg = event->attr.config & AMD_POWER_EVENT_MASK;
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/* Only look at AMD power events. */
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if (event->attr.type != pmu_class.type)
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return -ENOENT;
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/* Unsupported modes and filters. */
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if (event->attr.exclude_user ||
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event->attr.exclude_kernel ||
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event->attr.exclude_hv ||
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event->attr.exclude_idle ||
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event->attr.exclude_host ||
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event->attr.exclude_guest ||
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/* no sampling */
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event->attr.sample_period)
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return -EINVAL;
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if (cfg != AMD_POWER_EVENTSEL_PKG)
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return -EINVAL;
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return 0;
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}
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static void pmu_event_read(struct perf_event *event)
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{
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event_update(event);
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}
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static ssize_t
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get_attr_cpumask(struct device *dev, struct device_attribute *attr, char *buf)
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{
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return cpumap_print_to_pagebuf(true, buf, &cpu_mask);
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}
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static DEVICE_ATTR(cpumask, S_IRUGO, get_attr_cpumask, NULL);
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static struct attribute *pmu_attrs[] = {
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&dev_attr_cpumask.attr,
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NULL,
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};
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static struct attribute_group pmu_attr_group = {
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.attrs = pmu_attrs,
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};
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/*
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* Currently it only supports to report the power of each
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* processor/package.
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*/
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EVENT_ATTR_STR(power-pkg, power_pkg, "event=0x01");
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EVENT_ATTR_STR(power-pkg.unit, power_pkg_unit, "mWatts");
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/* Convert the count from micro-Watts to milli-Watts. */
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EVENT_ATTR_STR(power-pkg.scale, power_pkg_scale, "1.000000e-3");
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static struct attribute *events_attr[] = {
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EVENT_PTR(power_pkg),
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EVENT_PTR(power_pkg_unit),
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EVENT_PTR(power_pkg_scale),
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NULL,
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};
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static struct attribute_group pmu_events_group = {
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.name = "events",
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.attrs = events_attr,
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};
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PMU_FORMAT_ATTR(event, "config:0-7");
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static struct attribute *formats_attr[] = {
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&format_attr_event.attr,
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NULL,
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};
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static struct attribute_group pmu_format_group = {
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.name = "format",
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.attrs = formats_attr,
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};
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static const struct attribute_group *attr_groups[] = {
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&pmu_attr_group,
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&pmu_format_group,
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&pmu_events_group,
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NULL,
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};
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static struct pmu pmu_class = {
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.attr_groups = attr_groups,
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/* system-wide only */
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.task_ctx_nr = perf_invalid_context,
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.event_init = pmu_event_init,
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.add = pmu_event_add,
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.del = pmu_event_del,
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.start = pmu_event_start,
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.stop = pmu_event_stop,
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.read = pmu_event_read,
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};
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static int power_cpu_exit(unsigned int cpu)
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{
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int target;
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if (!cpumask_test_and_clear_cpu(cpu, &cpu_mask))
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return 0;
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/*
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* Find a new CPU on the same compute unit, if was set in cpumask
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* and still some CPUs on compute unit. Then migrate event and
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* context to new CPU.
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*/
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target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
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if (target < nr_cpumask_bits) {
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cpumask_set_cpu(target, &cpu_mask);
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perf_pmu_migrate_context(&pmu_class, cpu, target);
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}
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return 0;
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}
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static int power_cpu_init(unsigned int cpu)
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{
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int target;
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/*
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* 1) If any CPU is set at cpu_mask in the same compute unit, do
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* nothing.
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* 2) If no CPU is set at cpu_mask in the same compute unit,
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* set current ONLINE CPU.
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*
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* Note: if there is a CPU aside of the new one already in the
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* sibling mask, then it is also in cpu_mask.
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*/
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target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
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if (target >= nr_cpumask_bits)
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cpumask_set_cpu(cpu, &cpu_mask);
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return 0;
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}
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static const struct x86_cpu_id cpu_match[] = {
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{ .vendor = X86_VENDOR_AMD, .family = 0x15 },
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{},
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};
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static int __init amd_power_pmu_init(void)
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{
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int ret;
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if (!x86_match_cpu(cpu_match))
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return -ENODEV;
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if (!boot_cpu_has(X86_FEATURE_ACC_POWER))
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return -ENODEV;
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cpu_pwr_sample_ratio = cpuid_ecx(0x80000007);
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if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &max_cu_acc_power)) {
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pr_err("Failed to read max compute unit power accumulator MSR\n");
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return -ENODEV;
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}
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cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_POWER_ONLINE,
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"perf/x86/amd/power:online",
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power_cpu_init, power_cpu_exit);
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ret = perf_pmu_register(&pmu_class, "power", -1);
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if (WARN_ON(ret)) {
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pr_warn("AMD Power PMU registration failed\n");
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return ret;
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}
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pr_info("AMD Power PMU detected\n");
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return ret;
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}
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module_init(amd_power_pmu_init);
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static void __exit amd_power_pmu_exit(void)
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{
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cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_AMD_POWER_ONLINE);
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perf_pmu_unregister(&pmu_class);
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}
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module_exit(amd_power_pmu_exit);
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MODULE_AUTHOR("Huang Rui <ray.huang@amd.com>");
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MODULE_DESCRIPTION("AMD Processor Power Reporting Mechanism");
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MODULE_LICENSE("GPL v2");
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