/*
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* Copyright (C) 2013 Advanced Micro Devices, Inc.
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*
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* Author: Steven Kinney <Steven.Kinney@amd.com>
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* Author: Suravee Suthikulpanit <Suraveee.Suthikulpanit@amd.com>
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*
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* Perf: amd_iommu - AMD IOMMU Performance Counter PMU implementation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) "perf/amd_iommu: " fmt
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#include <linux/perf_event.h>
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#include <linux/init.h>
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#include <linux/cpumask.h>
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#include <linux/slab.h>
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#include "../perf_event.h"
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#include "iommu.h"
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#define COUNTER_SHIFT 16
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/* iommu pmu conf masks */
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#define GET_CSOURCE(x) ((x)->conf & 0xFFULL)
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#define GET_DEVID(x) (((x)->conf >> 8) & 0xFFFFULL)
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#define GET_DOMID(x) (((x)->conf >> 24) & 0xFFFFULL)
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#define GET_PASID(x) (((x)->conf >> 40) & 0xFFFFFULL)
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/* iommu pmu conf1 masks */
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#define GET_DEVID_MASK(x) ((x)->conf1 & 0xFFFFULL)
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#define GET_DOMID_MASK(x) (((x)->conf1 >> 16) & 0xFFFFULL)
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#define GET_PASID_MASK(x) (((x)->conf1 >> 32) & 0xFFFFFULL)
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#define IOMMU_NAME_SIZE 16
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struct perf_amd_iommu {
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struct list_head list;
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struct pmu pmu;
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struct amd_iommu *iommu;
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char name[IOMMU_NAME_SIZE];
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u8 max_banks;
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u8 max_counters;
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u64 cntr_assign_mask;
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raw_spinlock_t lock;
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};
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static LIST_HEAD(perf_amd_iommu_list);
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/*---------------------------------------------
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* sysfs format attributes
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*---------------------------------------------*/
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PMU_FORMAT_ATTR(csource, "config:0-7");
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PMU_FORMAT_ATTR(devid, "config:8-23");
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PMU_FORMAT_ATTR(domid, "config:24-39");
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PMU_FORMAT_ATTR(pasid, "config:40-59");
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PMU_FORMAT_ATTR(devid_mask, "config1:0-15");
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PMU_FORMAT_ATTR(domid_mask, "config1:16-31");
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PMU_FORMAT_ATTR(pasid_mask, "config1:32-51");
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static struct attribute *iommu_format_attrs[] = {
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&format_attr_csource.attr,
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&format_attr_devid.attr,
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&format_attr_pasid.attr,
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&format_attr_domid.attr,
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&format_attr_devid_mask.attr,
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&format_attr_pasid_mask.attr,
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&format_attr_domid_mask.attr,
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NULL,
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};
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static struct attribute_group amd_iommu_format_group = {
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.name = "format",
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.attrs = iommu_format_attrs,
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};
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/*---------------------------------------------
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* sysfs events attributes
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*---------------------------------------------*/
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static struct attribute_group amd_iommu_events_group = {
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.name = "events",
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};
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struct amd_iommu_event_desc {
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struct device_attribute attr;
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const char *event;
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};
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static ssize_t _iommu_event_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct amd_iommu_event_desc *event =
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container_of(attr, struct amd_iommu_event_desc, attr);
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return sprintf(buf, "%s\n", event->event);
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}
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#define AMD_IOMMU_EVENT_DESC(_name, _event) \
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{ \
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.attr = __ATTR(_name, 0444, _iommu_event_show, NULL), \
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.event = _event, \
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}
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static struct amd_iommu_event_desc amd_iommu_v2_event_descs[] = {
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AMD_IOMMU_EVENT_DESC(mem_pass_untrans, "csource=0x01"),
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AMD_IOMMU_EVENT_DESC(mem_pass_pretrans, "csource=0x02"),
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AMD_IOMMU_EVENT_DESC(mem_pass_excl, "csource=0x03"),
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AMD_IOMMU_EVENT_DESC(mem_target_abort, "csource=0x04"),
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AMD_IOMMU_EVENT_DESC(mem_trans_total, "csource=0x05"),
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AMD_IOMMU_EVENT_DESC(mem_iommu_tlb_pte_hit, "csource=0x06"),
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AMD_IOMMU_EVENT_DESC(mem_iommu_tlb_pte_mis, "csource=0x07"),
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AMD_IOMMU_EVENT_DESC(mem_iommu_tlb_pde_hit, "csource=0x08"),
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AMD_IOMMU_EVENT_DESC(mem_iommu_tlb_pde_mis, "csource=0x09"),
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AMD_IOMMU_EVENT_DESC(mem_dte_hit, "csource=0x0a"),
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AMD_IOMMU_EVENT_DESC(mem_dte_mis, "csource=0x0b"),
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AMD_IOMMU_EVENT_DESC(page_tbl_read_tot, "csource=0x0c"),
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AMD_IOMMU_EVENT_DESC(page_tbl_read_nst, "csource=0x0d"),
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AMD_IOMMU_EVENT_DESC(page_tbl_read_gst, "csource=0x0e"),
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AMD_IOMMU_EVENT_DESC(int_dte_hit, "csource=0x0f"),
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AMD_IOMMU_EVENT_DESC(int_dte_mis, "csource=0x10"),
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AMD_IOMMU_EVENT_DESC(cmd_processed, "csource=0x11"),
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AMD_IOMMU_EVENT_DESC(cmd_processed_inv, "csource=0x12"),
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AMD_IOMMU_EVENT_DESC(tlb_inv, "csource=0x13"),
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AMD_IOMMU_EVENT_DESC(ign_rd_wr_mmio_1ff8h, "csource=0x14"),
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AMD_IOMMU_EVENT_DESC(vapic_int_non_guest, "csource=0x15"),
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AMD_IOMMU_EVENT_DESC(vapic_int_guest, "csource=0x16"),
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AMD_IOMMU_EVENT_DESC(smi_recv, "csource=0x17"),
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AMD_IOMMU_EVENT_DESC(smi_blk, "csource=0x18"),
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{ /* end: all zeroes */ },
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};
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/*---------------------------------------------
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* sysfs cpumask attributes
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*---------------------------------------------*/
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static cpumask_t iommu_cpumask;
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static ssize_t _iommu_cpumask_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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return cpumap_print_to_pagebuf(true, buf, &iommu_cpumask);
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}
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static DEVICE_ATTR(cpumask, S_IRUGO, _iommu_cpumask_show, NULL);
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static struct attribute *iommu_cpumask_attrs[] = {
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&dev_attr_cpumask.attr,
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NULL,
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};
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static struct attribute_group amd_iommu_cpumask_group = {
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.attrs = iommu_cpumask_attrs,
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};
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/*---------------------------------------------*/
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static int get_next_avail_iommu_bnk_cntr(struct perf_event *event)
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{
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struct perf_amd_iommu *piommu = container_of(event->pmu, struct perf_amd_iommu, pmu);
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int max_cntrs = piommu->max_counters;
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int max_banks = piommu->max_banks;
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u32 shift, bank, cntr;
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unsigned long flags;
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int retval;
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raw_spin_lock_irqsave(&piommu->lock, flags);
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for (bank = 0, shift = 0; bank < max_banks; bank++) {
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for (cntr = 0; cntr < max_cntrs; cntr++) {
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shift = bank + (bank*3) + cntr;
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if (piommu->cntr_assign_mask & BIT_ULL(shift)) {
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continue;
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} else {
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piommu->cntr_assign_mask |= BIT_ULL(shift);
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event->hw.iommu_bank = bank;
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event->hw.iommu_cntr = cntr;
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retval = 0;
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goto out;
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}
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}
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}
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retval = -ENOSPC;
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out:
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raw_spin_unlock_irqrestore(&piommu->lock, flags);
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return retval;
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}
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static int clear_avail_iommu_bnk_cntr(struct perf_amd_iommu *perf_iommu,
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u8 bank, u8 cntr)
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{
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unsigned long flags;
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int max_banks, max_cntrs;
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int shift = 0;
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max_banks = perf_iommu->max_banks;
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max_cntrs = perf_iommu->max_counters;
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if ((bank > max_banks) || (cntr > max_cntrs))
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return -EINVAL;
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shift = bank + cntr + (bank*3);
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raw_spin_lock_irqsave(&perf_iommu->lock, flags);
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perf_iommu->cntr_assign_mask &= ~(1ULL<<shift);
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raw_spin_unlock_irqrestore(&perf_iommu->lock, flags);
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return 0;
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}
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static int perf_iommu_event_init(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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/* test the event attr type check for PMU enumeration */
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if (event->attr.type != event->pmu->type)
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return -ENOENT;
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/*
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* IOMMU counters are shared across all cores.
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* Therefore, it does not support per-process mode.
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* Also, it does not support event sampling mode.
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*/
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if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
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return -EINVAL;
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/* IOMMU counters do not have usr/os/guest/host bits */
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if (event->attr.exclude_user || event->attr.exclude_kernel ||
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event->attr.exclude_host || event->attr.exclude_guest)
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return -EINVAL;
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if (event->cpu < 0)
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return -EINVAL;
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/* update the hw_perf_event struct with the iommu config data */
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hwc->conf = event->attr.config;
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hwc->conf1 = event->attr.config1;
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return 0;
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}
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static inline struct amd_iommu *perf_event_2_iommu(struct perf_event *ev)
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{
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return (container_of(ev->pmu, struct perf_amd_iommu, pmu))->iommu;
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}
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static void perf_iommu_enable_event(struct perf_event *ev)
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{
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struct amd_iommu *iommu = perf_event_2_iommu(ev);
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struct hw_perf_event *hwc = &ev->hw;
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u8 bank = hwc->iommu_bank;
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u8 cntr = hwc->iommu_cntr;
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u64 reg = 0ULL;
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reg = GET_CSOURCE(hwc);
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amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_COUNTER_SRC_REG, ®);
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reg = GET_DEVID_MASK(hwc);
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reg = GET_DEVID(hwc) | (reg << 32);
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if (reg)
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reg |= BIT(31);
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amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DEVID_MATCH_REG, ®);
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reg = GET_PASID_MASK(hwc);
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reg = GET_PASID(hwc) | (reg << 32);
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if (reg)
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reg |= BIT(31);
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amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_PASID_MATCH_REG, ®);
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reg = GET_DOMID_MASK(hwc);
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reg = GET_DOMID(hwc) | (reg << 32);
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if (reg)
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reg |= BIT(31);
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amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DOMID_MATCH_REG, ®);
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}
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static void perf_iommu_disable_event(struct perf_event *event)
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{
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struct amd_iommu *iommu = perf_event_2_iommu(event);
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struct hw_perf_event *hwc = &event->hw;
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u64 reg = 0ULL;
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amd_iommu_pc_set_reg(iommu, hwc->iommu_bank, hwc->iommu_cntr,
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IOMMU_PC_COUNTER_SRC_REG, ®);
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}
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static void perf_iommu_start(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
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return;
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WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
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hwc->state = 0;
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if (flags & PERF_EF_RELOAD) {
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u64 prev_raw_count = local64_read(&hwc->prev_count);
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struct amd_iommu *iommu = perf_event_2_iommu(event);
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amd_iommu_pc_set_reg(iommu, hwc->iommu_bank, hwc->iommu_cntr,
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IOMMU_PC_COUNTER_REG, &prev_raw_count);
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}
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perf_iommu_enable_event(event);
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perf_event_update_userpage(event);
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}
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static void perf_iommu_read(struct perf_event *event)
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{
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u64 count, prev, delta;
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struct hw_perf_event *hwc = &event->hw;
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struct amd_iommu *iommu = perf_event_2_iommu(event);
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if (amd_iommu_pc_get_reg(iommu, hwc->iommu_bank, hwc->iommu_cntr,
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IOMMU_PC_COUNTER_REG, &count))
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return;
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/* IOMMU pc counter register is only 48 bits */
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count &= GENMASK_ULL(47, 0);
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prev = local64_read(&hwc->prev_count);
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if (local64_cmpxchg(&hwc->prev_count, prev, count) != prev)
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return;
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/* Handle 48-bit counter overflow */
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delta = (count << COUNTER_SHIFT) - (prev << COUNTER_SHIFT);
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delta >>= COUNTER_SHIFT;
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local64_add(delta, &event->count);
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}
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static void perf_iommu_stop(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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if (hwc->state & PERF_HES_UPTODATE)
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return;
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perf_iommu_disable_event(event);
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WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
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hwc->state |= PERF_HES_STOPPED;
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if (hwc->state & PERF_HES_UPTODATE)
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return;
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perf_iommu_read(event);
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hwc->state |= PERF_HES_UPTODATE;
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}
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static int perf_iommu_add(struct perf_event *event, int flags)
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{
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int retval;
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event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
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/* request an iommu bank/counter */
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retval = get_next_avail_iommu_bnk_cntr(event);
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if (retval)
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return retval;
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if (flags & PERF_EF_START)
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perf_iommu_start(event, PERF_EF_RELOAD);
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return 0;
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}
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static void perf_iommu_del(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct perf_amd_iommu *perf_iommu =
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container_of(event->pmu, struct perf_amd_iommu, pmu);
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perf_iommu_stop(event, PERF_EF_UPDATE);
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/* clear the assigned iommu bank/counter */
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clear_avail_iommu_bnk_cntr(perf_iommu,
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hwc->iommu_bank, hwc->iommu_cntr);
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perf_event_update_userpage(event);
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}
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static __init int _init_events_attrs(void)
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{
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int i = 0, j;
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struct attribute **attrs;
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while (amd_iommu_v2_event_descs[i].attr.attr.name)
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i++;
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attrs = kcalloc(i + 1, sizeof(*attrs), GFP_KERNEL);
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if (!attrs)
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return -ENOMEM;
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for (j = 0; j < i; j++)
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attrs[j] = &amd_iommu_v2_event_descs[j].attr.attr;
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amd_iommu_events_group.attrs = attrs;
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return 0;
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}
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const struct attribute_group *amd_iommu_attr_groups[] = {
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&amd_iommu_format_group,
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&amd_iommu_cpumask_group,
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&amd_iommu_events_group,
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NULL,
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};
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static const struct pmu iommu_pmu __initconst = {
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.event_init = perf_iommu_event_init,
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.add = perf_iommu_add,
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.del = perf_iommu_del,
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.start = perf_iommu_start,
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.stop = perf_iommu_stop,
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.read = perf_iommu_read,
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.task_ctx_nr = perf_invalid_context,
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.attr_groups = amd_iommu_attr_groups,
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};
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static __init int init_one_iommu(unsigned int idx)
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{
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struct perf_amd_iommu *perf_iommu;
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int ret;
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perf_iommu = kzalloc(sizeof(struct perf_amd_iommu), GFP_KERNEL);
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if (!perf_iommu)
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return -ENOMEM;
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raw_spin_lock_init(&perf_iommu->lock);
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perf_iommu->pmu = iommu_pmu;
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perf_iommu->iommu = get_amd_iommu(idx);
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perf_iommu->max_banks = amd_iommu_pc_get_max_banks(idx);
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perf_iommu->max_counters = amd_iommu_pc_get_max_counters(idx);
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if (!perf_iommu->iommu ||
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!perf_iommu->max_banks ||
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!perf_iommu->max_counters) {
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kfree(perf_iommu);
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return -EINVAL;
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}
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snprintf(perf_iommu->name, IOMMU_NAME_SIZE, "amd_iommu_%u", idx);
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ret = perf_pmu_register(&perf_iommu->pmu, perf_iommu->name, -1);
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if (!ret) {
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pr_info("Detected AMD IOMMU #%d (%d banks, %d counters/bank).\n",
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idx, perf_iommu->max_banks, perf_iommu->max_counters);
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list_add_tail(&perf_iommu->list, &perf_amd_iommu_list);
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} else {
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pr_warn("Error initializing IOMMU %d.\n", idx);
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kfree(perf_iommu);
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}
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return ret;
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}
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static __init int amd_iommu_pc_init(void)
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{
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unsigned int i, cnt = 0;
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int ret;
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/* Make sure the IOMMU PC resource is available */
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if (!amd_iommu_pc_supported())
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return -ENODEV;
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ret = _init_events_attrs();
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if (ret)
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return ret;
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/*
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* An IOMMU PMU is specific to an IOMMU, and can function independently.
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* So we go through all IOMMUs and ignore the one that fails init
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* unless all IOMMU are failing.
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*/
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for (i = 0; i < amd_iommu_get_num_iommus(); i++) {
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ret = init_one_iommu(i);
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if (!ret)
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cnt++;
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}
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if (!cnt) {
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kfree(amd_iommu_events_group.attrs);
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return -ENODEV;
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}
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/* Init cpumask attributes to only core 0 */
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cpumask_set_cpu(0, &iommu_cpumask);
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return 0;
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}
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device_initcall(amd_iommu_pc_init);
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