/*
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* Flush routine for SHA1 multibuffer
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2014 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* Contact Information:
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* James Guilford <james.guilford@intel.com>
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* Tim Chen <tim.c.chen@linux.intel.com>
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*
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* BSD LICENSE
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*
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* Copyright(c) 2014 Intel Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/linkage.h>
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#include <asm/frame.h>
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#include "sha1_mb_mgr_datastruct.S"
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.extern sha1_x8_avx2
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# LINUX register definitions
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#define arg1 %rdi
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#define arg2 %rsi
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# Common definitions
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#define state arg1
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#define job arg2
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#define len2 arg2
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# idx must be a register not clobbered by sha1_x8_avx2
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#define idx %r8
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#define DWORD_idx %r8d
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#define unused_lanes %rbx
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#define lane_data %rbx
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#define tmp2 %rbx
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#define tmp2_w %ebx
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#define job_rax %rax
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#define tmp1 %rax
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#define size_offset %rax
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#define tmp %rax
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#define start_offset %rax
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#define tmp3 %arg1
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#define extra_blocks %arg2
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#define p %arg2
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.macro LABEL prefix n
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\prefix\n\():
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.endm
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.macro JNE_SKIP i
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jne skip_\i
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.endm
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.altmacro
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.macro SET_OFFSET _offset
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offset = \_offset
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.endm
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.noaltmacro
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# JOB* sha1_mb_mgr_flush_avx2(MB_MGR *state)
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# arg 1 : rcx : state
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ENTRY(sha1_mb_mgr_flush_avx2)
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FRAME_BEGIN
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push %rbx
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# If bit (32+3) is set, then all lanes are empty
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mov _unused_lanes(state), unused_lanes
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bt $32+3, unused_lanes
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jc return_null
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# find a lane with a non-null job
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xor idx, idx
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offset = (_ldata + 1 * _LANE_DATA_size + _job_in_lane)
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cmpq $0, offset(state)
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cmovne one(%rip), idx
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offset = (_ldata + 2 * _LANE_DATA_size + _job_in_lane)
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cmpq $0, offset(state)
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cmovne two(%rip), idx
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offset = (_ldata + 3 * _LANE_DATA_size + _job_in_lane)
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cmpq $0, offset(state)
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cmovne three(%rip), idx
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offset = (_ldata + 4 * _LANE_DATA_size + _job_in_lane)
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cmpq $0, offset(state)
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cmovne four(%rip), idx
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offset = (_ldata + 5 * _LANE_DATA_size + _job_in_lane)
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cmpq $0, offset(state)
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cmovne five(%rip), idx
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offset = (_ldata + 6 * _LANE_DATA_size + _job_in_lane)
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cmpq $0, offset(state)
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cmovne six(%rip), idx
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offset = (_ldata + 7 * _LANE_DATA_size + _job_in_lane)
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cmpq $0, offset(state)
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cmovne seven(%rip), idx
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# copy idx to empty lanes
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copy_lane_data:
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offset = (_args + _data_ptr)
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mov offset(state,idx,8), tmp
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I = 0
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.rep 8
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offset = (_ldata + I * _LANE_DATA_size + _job_in_lane)
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cmpq $0, offset(state)
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.altmacro
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JNE_SKIP %I
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offset = (_args + _data_ptr + 8*I)
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mov tmp, offset(state)
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offset = (_lens + 4*I)
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movl $0xFFFFFFFF, offset(state)
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LABEL skip_ %I
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I = (I+1)
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.noaltmacro
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.endr
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# Find min length
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vmovdqu _lens+0*16(state), %xmm0
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vmovdqu _lens+1*16(state), %xmm1
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vpminud %xmm1, %xmm0, %xmm2 # xmm2 has {D,C,B,A}
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vpalignr $8, %xmm2, %xmm3, %xmm3 # xmm3 has {x,x,D,C}
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vpminud %xmm3, %xmm2, %xmm2 # xmm2 has {x,x,E,F}
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vpalignr $4, %xmm2, %xmm3, %xmm3 # xmm3 has {x,x,x,E}
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vpminud %xmm3, %xmm2, %xmm2 # xmm2 has min value in low dword
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vmovd %xmm2, DWORD_idx
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mov idx, len2
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and $0xF, idx
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shr $4, len2
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jz len_is_0
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vpand clear_low_nibble(%rip), %xmm2, %xmm2
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vpshufd $0, %xmm2, %xmm2
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vpsubd %xmm2, %xmm0, %xmm0
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vpsubd %xmm2, %xmm1, %xmm1
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vmovdqu %xmm0, _lens+0*16(state)
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vmovdqu %xmm1, _lens+1*16(state)
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# "state" and "args" are the same address, arg1
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# len is arg2
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call sha1_x8_avx2
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# state and idx are intact
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len_is_0:
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# process completed job "idx"
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imul $_LANE_DATA_size, idx, lane_data
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lea _ldata(state, lane_data), lane_data
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mov _job_in_lane(lane_data), job_rax
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movq $0, _job_in_lane(lane_data)
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movl $STS_COMPLETED, _status(job_rax)
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mov _unused_lanes(state), unused_lanes
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shl $4, unused_lanes
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or idx, unused_lanes
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mov unused_lanes, _unused_lanes(state)
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movl $0xFFFFFFFF, _lens(state, idx, 4)
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vmovd _args_digest(state , idx, 4) , %xmm0
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vpinsrd $1, _args_digest+1*32(state, idx, 4), %xmm0, %xmm0
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vpinsrd $2, _args_digest+2*32(state, idx, 4), %xmm0, %xmm0
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vpinsrd $3, _args_digest+3*32(state, idx, 4), %xmm0, %xmm0
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movl _args_digest+4*32(state, idx, 4), tmp2_w
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vmovdqu %xmm0, _result_digest(job_rax)
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offset = (_result_digest + 1*16)
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mov tmp2_w, offset(job_rax)
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return:
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pop %rbx
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FRAME_END
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ret
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return_null:
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xor job_rax, job_rax
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jmp return
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ENDPROC(sha1_mb_mgr_flush_avx2)
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#################################################################
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.align 16
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ENTRY(sha1_mb_mgr_get_comp_job_avx2)
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push %rbx
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## if bit 32+3 is set, then all lanes are empty
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mov _unused_lanes(state), unused_lanes
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bt $(32+3), unused_lanes
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jc .return_null
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# Find min length
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vmovdqu _lens(state), %xmm0
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vmovdqu _lens+1*16(state), %xmm1
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vpminud %xmm1, %xmm0, %xmm2 # xmm2 has {D,C,B,A}
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vpalignr $8, %xmm2, %xmm3, %xmm3 # xmm3 has {x,x,D,C}
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vpminud %xmm3, %xmm2, %xmm2 # xmm2 has {x,x,E,F}
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vpalignr $4, %xmm2, %xmm3, %xmm3 # xmm3 has {x,x,x,E}
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vpminud %xmm3, %xmm2, %xmm2 # xmm2 has min value in low dword
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vmovd %xmm2, DWORD_idx
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test $~0xF, idx
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jnz .return_null
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# process completed job "idx"
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imul $_LANE_DATA_size, idx, lane_data
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lea _ldata(state, lane_data), lane_data
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mov _job_in_lane(lane_data), job_rax
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movq $0, _job_in_lane(lane_data)
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movl $STS_COMPLETED, _status(job_rax)
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mov _unused_lanes(state), unused_lanes
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shl $4, unused_lanes
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or idx, unused_lanes
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mov unused_lanes, _unused_lanes(state)
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movl $0xFFFFFFFF, _lens(state, idx, 4)
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vmovd _args_digest(state, idx, 4), %xmm0
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vpinsrd $1, _args_digest+1*32(state, idx, 4), %xmm0, %xmm0
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vpinsrd $2, _args_digest+2*32(state, idx, 4), %xmm0, %xmm0
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vpinsrd $3, _args_digest+3*32(state, idx, 4), %xmm0, %xmm0
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movl _args_digest+4*32(state, idx, 4), tmp2_w
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vmovdqu %xmm0, _result_digest(job_rax)
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movl tmp2_w, _result_digest+1*16(job_rax)
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pop %rbx
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ret
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.return_null:
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xor job_rax, job_rax
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pop %rbx
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ret
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ENDPROC(sha1_mb_mgr_get_comp_job_avx2)
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.section .rodata.cst16.clear_low_nibble, "aM", @progbits, 16
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.align 16
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clear_low_nibble:
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.octa 0x000000000000000000000000FFFFFFF0
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.section .rodata.cst8, "aM", @progbits, 8
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.align 8
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one:
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.quad 1
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two:
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.quad 2
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three:
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.quad 3
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four:
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.quad 4
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five:
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.quad 5
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six:
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.quad 6
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seven:
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.quad 7
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