Renesas R-Car Fine Display Processor (FDP1)
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The FDP1 is a de-interlacing module which converts interlaced video to
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progressive video. It is capable of performing pixel format conversion between
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YCbCr/YUV formats and RGB formats. Only YCbCr/YUV formats are supported as
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an input to the module.
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Required properties:
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- compatible: must be "renesas,fdp1"
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- reg: the register base and size for the device registers
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- interrupts : interrupt specifier for the FDP1 instance
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- clocks: reference to the functional clock
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Optional properties:
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- power-domains: reference to the power domain that the FDP1 belongs to, if
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any.
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- renesas,fcp: a phandle referencing the FCP that handles memory accesses
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for the FDP1. Not needed on Gen2, mandatory on Gen3.
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Please refer to the binding documentation for the clock and/or power domain
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providers for more details.
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Device node example
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-------------------
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fdp1@fe940000 {
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compatible = "renesas,fdp1";
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reg = <0 0xfe940000 0 0x2400>;
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interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 119>;
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power-domains = <&sysc R8A7795_PD_A3VP>;
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renesas,fcp = <&fcpf0>;
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};
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