Allwinner A31 DSI Encoder
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=========================
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The DSI pipeline consists of two separate blocks: the DSI controller
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itself, and its associated D-PHY.
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DSI Encoder
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-----------
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The DSI Encoder generates the DSI signal from the TCON's.
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Required properties:
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- compatible: value must be one of:
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* allwinner,sun6i-a31-mipi-dsi
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- reg: base address and size of memory-mapped region
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- interrupts: interrupt associated to this IP
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- clocks: phandles to the clocks feeding the DSI encoder
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* bus: the DSI interface clock
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* mod: the DSI module clock
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- clock-names: the clock names mentioned above
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- phys: phandle to the D-PHY
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- phy-names: must be "dphy"
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- resets: phandle to the reset controller driving the encoder
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- ports: A ports node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoint, usually coming from the
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associated TCON.
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Any MIPI-DSI device attached to this should be described according to
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the bindings defined in ../mipi-dsi-bus.txt
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D-PHY
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-----
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Required properties:
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- compatible: value must be one of:
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* allwinner,sun6i-a31-mipi-dphy
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- reg: base address and size of memory-mapped region
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- clocks: phandles to the clocks feeding the DSI encoder
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* bus: the DSI interface clock
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* mod: the DSI module clock
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- clock-names: the clock names mentioned above
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- resets: phandle to the reset controller driving the encoder
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Example:
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dsi0: dsi@1ca0000 {
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compatible = "allwinner,sun6i-a31-mipi-dsi";
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reg = <0x01ca0000 0x1000>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_MIPI_DSI>,
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<&ccu CLK_DSI_SCLK>;
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clock-names = "bus", "mod";
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resets = <&ccu RST_BUS_MIPI_DSI>;
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phys = <&dphy0>;
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phy-names = "dphy";
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#address-cells = <1>;
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#size-cells = <0>;
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panel@0 {
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compatible = "bananapi,lhr050h41", "ilitek,ili9881c";
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reg = <0>;
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power-gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; /* PB07 */
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reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */
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backlight = <&pwm_bl>;
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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dsi0_in_tcon0: endpoint {
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remote-endpoint = <&tcon0_out_dsi0>;
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};
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};
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};
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};
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dphy0: d-phy@1ca1000 {
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compatible = "allwinner,sun6i-a31-mipi-dphy";
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reg = <0x01ca1000 0x1000>;
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clocks = <&ccu CLK_BUS_MIPI_DSI>,
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<&ccu CLK_DSI_DPHY>;
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clock-names = "bus", "mod";
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resets = <&ccu RST_BUS_MIPI_DSI>;
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#phy-cells = <0>;
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};
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