# SPDX-License-Identifier: GPL-2.0
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#
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# Rockchip Clock specific Makefile
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#
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obj-y += clk.o
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obj-y += clk-pll.o
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obj-y += clk-cpu.o
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obj-y += clk-half-divider.o
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obj-y += clk-mmc-phase.o
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obj-y += clk-muxgrf.o
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obj-y += clk-ddr.o
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obj-$(CONFIG_ROCKCHIP_CLK_INV) += clk-inverter.o
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obj-$(CONFIG_ROCKCHIP_CLK_PVTM) += clk-pvtm.o
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obj-$(CONFIG_ROCKCHIP_DCLK_DIV) += clk-dclk-divider.o
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obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
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obj-$(CONFIG_CPU_PX30) += clk-px30.o
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obj-$(CONFIG_CPU_RV110X) += clk-rv1108.o
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obj-$(CONFIG_CPU_RV1126) += clk-rv1126.o
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obj-$(CONFIG_CPU_RK1808) += clk-rk1808.o
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obj-$(CONFIG_CPU_RK3036) += clk-rk3036.o
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obj-$(CONFIG_CPU_RK312X) += clk-rk3128.o
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obj-$(CONFIG_CPU_RK3188) += clk-rk3188.o
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obj-$(CONFIG_CPU_RK322X) += clk-rk3228.o
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obj-$(CONFIG_CPU_RK3288) += clk-rk3288.o
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obj-$(CONFIG_CPU_RK3308) += clk-rk3308.o
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obj-$(CONFIG_CPU_RK3328) += clk-rk3328.o
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obj-$(CONFIG_CPU_RK3368) += clk-rk3368.o
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obj-$(CONFIG_CPU_RK3528) += clk-rk3528.o
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obj-$(CONFIG_CPU_RK3568) += clk-rk3568.o
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obj-$(CONFIG_CPU_RK3399) += clk-rk3399.o
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obj-$(CONFIG_COMMON_CLK_ROCKCHIP_REGMAP) += regmap/
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obj-$(CONFIG_ROCKCHIP_CLK_OUT) += clk-out.o
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