/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_SH_HITACHI_SE7343_H
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#define __ASM_SH_HITACHI_SE7343_H
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/*
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* include/asm-sh/se/se7343.h
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*
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* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
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*
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* SH-Mobile SolutionEngine 7343 support
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*/
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#include <linux/sh_intc.h>
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/* Box specific addresses. */
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/* Area 0 */
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#define PA_ROM 0x00000000 /* EPROM */
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#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
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#define PA_FROM 0x00400000 /* Flash ROM */
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#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
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#define PA_SRAM 0x00800000 /* SRAM */
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#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
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/* Area 1 */
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#define PA_EXT1 0x04000000
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#define PA_EXT1_SIZE 0x04000000
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/* Area 2 */
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#define PA_EXT2 0x08000000
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#define PA_EXT2_SIZE 0x04000000
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/* Area 3 */
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#define PA_SDRAM 0x0c000000
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#define PA_SDRAM_SIZE 0x04000000
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/* Area 4 */
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#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */
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#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */
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#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */
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#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */
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#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */
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#define MRSHPC_OPTION (PA_MRSHPC + 6)
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#define MRSHPC_CSR (PA_MRSHPC + 8)
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#define MRSHPC_ISR (PA_MRSHPC + 10)
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#define MRSHPC_ICR (PA_MRSHPC + 12)
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#define MRSHPC_CPWCR (PA_MRSHPC + 14)
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#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
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#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
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#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
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#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
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#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
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#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
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#define MRSHPC_CDCR (PA_MRSHPC + 28)
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#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
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#define PA_LED 0xb0C00000 /* LED */
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#define LED_SHIFT 0
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#define PA_DIPSW 0xb0900000 /* Dip switch 31 */
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/* Area 5 */
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#define PA_EXT5 0x14000000
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#define PA_EXT5_SIZE 0x04000000
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/* Area 6 */
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#define PA_LCD1 0xb8000000
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#define PA_LCD2 0xb8800000
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#define PORT_PACR 0xA4050100
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#define PORT_PBCR 0xA4050102
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#define PORT_PCCR 0xA4050104
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#define PORT_PDCR 0xA4050106
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#define PORT_PECR 0xA4050108
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#define PORT_PFCR 0xA405010A
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#define PORT_PGCR 0xA405010C
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#define PORT_PHCR 0xA405010E
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#define PORT_PJCR 0xA4050110
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#define PORT_PKCR 0xA4050112
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#define PORT_PLCR 0xA4050114
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#define PORT_PMCR 0xA4050116
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#define PORT_PNCR 0xA4050118
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#define PORT_PQCR 0xA405011A
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#define PORT_PRCR 0xA405011C
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#define PORT_PSCR 0xA405011E
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#define PORT_PTCR 0xA4050140
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#define PORT_PUCR 0xA4050142
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#define PORT_PVCR 0xA4050144
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#define PORT_PWCR 0xA4050146
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#define PORT_PYCR 0xA4050148
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#define PORT_PZCR 0xA405014A
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#define PORT_PSELA 0xA405014C
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#define PORT_PSELB 0xA405014E
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#define PORT_PSELC 0xA4050150
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#define PORT_PSELD 0xA4050152
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#define PORT_PSELE 0xA4050154
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#define PORT_HIZCRA 0xA4050156
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#define PORT_HIZCRB 0xA4050158
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#define PORT_HIZCRC 0xA405015C
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#define PORT_DRVCR 0xA4050180
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#define PORT_PADR 0xA4050120
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#define PORT_PBDR 0xA4050122
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#define PORT_PCDR 0xA4050124
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#define PORT_PDDR 0xA4050126
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#define PORT_PEDR 0xA4050128
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#define PORT_PFDR 0xA405012A
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#define PORT_PGDR 0xA405012C
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#define PORT_PHDR 0xA405012E
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#define PORT_PJDR 0xA4050130
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#define PORT_PKDR 0xA4050132
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#define PORT_PLDR 0xA4050134
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#define PORT_PMDR 0xA4050136
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#define PORT_PNDR 0xA4050138
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#define PORT_PQDR 0xA405013A
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#define PORT_PRDR 0xA405013C
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#define PORT_PTDR 0xA4050160
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#define PORT_PUDR 0xA4050162
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#define PORT_PVDR 0xA4050164
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#define PORT_PWDR 0xA4050166
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#define PORT_PYDR 0xA4050168
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#define FPGA_IN 0xb1400000
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#define FPGA_OUT 0xb1400002
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#define IRQ0_IRQ evt2irq(0x600)
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#define IRQ1_IRQ evt2irq(0x620)
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#define IRQ4_IRQ evt2irq(0x680)
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#define IRQ5_IRQ evt2irq(0x6a0)
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#define SE7343_FPGA_IRQ_MRSHPC0 0
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#define SE7343_FPGA_IRQ_MRSHPC1 1
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#define SE7343_FPGA_IRQ_MRSHPC2 2
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#define SE7343_FPGA_IRQ_MRSHPC3 3
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#define SE7343_FPGA_IRQ_SMC 6 /* EXT_IRQ2 */
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#define SE7343_FPGA_IRQ_USB 8
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#define SE7343_FPGA_IRQ_UARTA 10
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#define SE7343_FPGA_IRQ_UARTB 11
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#define SE7343_FPGA_IRQ_NR 12
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struct irq_domain;
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/* arch/sh/boards/se/7343/irq.c */
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extern struct irq_domain *se7343_irq_domain;
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void init_7343se_IRQ(void);
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#endif /* __ASM_SH_HITACHI_SE7343_H */
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