NVIDIA Tegra20 Clock And Reset Controller
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This binding uses the common clock binding:
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
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for muxing and gating Tegra's clocks, and setting their rates.
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Required properties :
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- compatible : Should be "nvidia,tegra20-car"
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- reg : Should contain CAR registers location and length
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- clocks : Should contain phandle and clock specifiers for two clocks:
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the 32 KHz "32k_in", and the board-specific oscillator "osc".
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- #clock-cells : Should be 1.
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In clock consumers, this cell represents the clock ID exposed by the CAR.
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The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
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registers. These IDs often match those in the CAR's RST_DEVICES registers,
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but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
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this case, those clocks are assigned IDs above 95 in order to highlight
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this issue. Implementations that interpret these clock IDs as bit values
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within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
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explicitly handle these special cases.
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The balance of the clocks controlled by the CAR are assigned IDs of 96 and
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above.
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0 cpu
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1 unassigned
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2 unassigned
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3 ac97
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4 rtc
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5 tmr
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6 uart1
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7 unassigned (register bit affects uart2 and vfir)
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8 gpio
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9 sdmmc2
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10 unassigned (register bit affects spdif_in and spdif_out)
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11 i2s1
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12 i2c1
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13 ndflash
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14 sdmmc1
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15 sdmmc4
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16 twc
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17 pwm
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18 i2s2
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19 epp
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20 unassigned (register bit affects vi and vi_sensor)
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21 2d
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22 usbd
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23 isp
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24 3d
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25 ide
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26 disp2
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27 disp1
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28 host1x
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29 vcp
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30 unassigned
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31 cache2
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32 mem
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33 ahbdma
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34 apbdma
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35 unassigned
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36 kbc
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37 stat_mon
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38 pmc
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39 fuse
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40 kfuse
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41 sbc1
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42 snor
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43 spi1
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44 sbc2
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45 xio
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46 sbc3
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47 dvc
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48 dsi
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49 unassigned (register bit affects tvo and cve)
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50 mipi
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51 hdmi
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52 csi
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53 tvdac
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54 i2c2
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55 uart3
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56 unassigned
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57 emc
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58 usb2
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59 usb3
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60 mpe
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61 vde
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62 bsea
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63 bsev
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64 speedo
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65 uart4
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66 uart5
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67 i2c3
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68 sbc4
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69 sdmmc3
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70 pcie
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71 owr
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72 afi
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73 csite
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74 unassigned
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75 avpucq
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76 la
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77 unassigned
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78 unassigned
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79 unassigned
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80 unassigned
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81 unassigned
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82 unassigned
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83 unassigned
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84 irama
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85 iramb
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86 iramc
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87 iramd
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88 cram2
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89 audio_2x a/k/a audio_2x_sync_clk
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90 clk_d
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91 unassigned
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92 sus
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93 cdev1
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94 cdev2
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95 unassigned
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96 uart2
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97 vfir
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98 spdif_in
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99 spdif_out
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100 vi
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101 vi_sensor
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102 tvo
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103 cve
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104 osc
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105 clk_32k a/k/a clk_s
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106 clk_m
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107 sclk
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108 cclk
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109 hclk
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110 pclk
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111 blink
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112 pll_a
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113 pll_a_out0
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114 pll_c
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115 pll_c_out1
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116 pll_d
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117 pll_d_out0
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118 pll_e
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119 pll_m
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120 pll_m_out1
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121 pll_p
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122 pll_p_out1
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123 pll_p_out2
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124 pll_p_out3
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125 pll_p_out4
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126 pll_s
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127 pll_u
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128 pll_x
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129 cop a/k/a avp
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130 audio a/k/a audio_sync_clk
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Example SoC include file:
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/ {
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tegra_car: clock@60006000 {
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compatible = "nvidia,tegra20-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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};
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usb@c5004000 {
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clocks = <&tegra_car 58>; /* usb2 */
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};
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};
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Example board file:
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/ {
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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osc: clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12000000>;
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};
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};
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i2c@7000d000 {
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pmic@34 {
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compatible = "ti,tps6586x";
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reg = <0x34>;
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clk_32k: clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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};
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&tegra_car {
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clocks = <&clk_32k> <&osc>;
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};
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};
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