// SPDX-License-Identifier: GPL-2.0
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/*
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* DPAA2 Ethernet Switch declarations
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*
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* Copyright 2014-2016 Freescale Semiconductor Inc.
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* Copyright 2017-2018 NXP
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*
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*/
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#ifndef __ETHSW_H
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#define __ETHSW_H
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/rtnetlink.h>
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#include <linux/if_vlan.h>
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#include <uapi/linux/if_bridge.h>
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#include <net/switchdev.h>
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#include <linux/if_bridge.h>
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#include "dpsw.h"
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/* Number of IRQs supported */
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#define DPSW_IRQ_NUM 2
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#define ETHSW_VLAN_MEMBER 1
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#define ETHSW_VLAN_UNTAGGED 2
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#define ETHSW_VLAN_PVID 4
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#define ETHSW_VLAN_GLOBAL 8
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/* Maximum Frame Length supported by HW (currently 10k) */
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#define DPAA2_MFL (10 * 1024)
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#define ETHSW_MAX_FRAME_LENGTH (DPAA2_MFL - VLAN_ETH_HLEN - ETH_FCS_LEN)
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#define ETHSW_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN + ETH_FCS_LEN)
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extern const struct ethtool_ops ethsw_port_ethtool_ops;
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struct ethsw_core;
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/* Per port private data */
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struct ethsw_port_priv {
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struct net_device *netdev;
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u16 idx;
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struct ethsw_core *ethsw_data;
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u8 link_state;
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u8 stp_state;
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bool flood;
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u8 vlans[VLAN_VID_MASK + 1];
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u16 pvid;
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struct net_device *bridge_dev;
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};
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/* Switch data */
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struct ethsw_core {
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struct device *dev;
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struct fsl_mc_io *mc_io;
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u16 dpsw_handle;
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struct dpsw_attr sw_attr;
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int dev_id;
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struct ethsw_port_priv **ports;
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u8 vlans[VLAN_VID_MASK + 1];
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bool learning;
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};
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#endif /* __ETHSW_H */
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