RPMH RSC:
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------------
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Resource Power Manager Hardened (RPMH) is the mechanism for communicating with
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the hardened resource accelerators on Qualcomm SoCs. Requests to the resources
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can be written to the Trigger Command Set (TCS) registers and using a (addr,
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val) pair and triggered. Messages in the TCS are then sent in sequence over an
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internal bus.
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The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
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(Resource State Coordinator a.k.a RSC) that can handle multiple sleep and
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active/wake resource requests. Multiple such DRVs can exist in a SoC and can
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be written to from Linux. The structure of each DRV follows the same template
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with a few variations that are captured by the properties here.
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A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
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have powered off to facilitate idle power saving. TCS could be classified as -
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ACTIVE /* Triggered by Linux */
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SLEEP /* Triggered by F/W */
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WAKE /* Triggered by F/W */
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CONTROL /* Triggered by F/W */
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The order in which they are described in the DT, should match the hardware
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configuration.
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Requests can be made for the state of a resource, when the subsystem is active
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or idle. When all subsystems like Modem, GPU, CPU are idle, the resource state
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will be an aggregate of the sleep votes from each of those subsystems. Clients
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may request a sleep value for their shared resources in addition to the active
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mode requests.
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Properties:
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- compatible:
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Usage: required
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Value type: <string>
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Definition: Should be "qcom,rpmh-rsc".
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: The first register specifies the base address of the
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DRV(s). The number of DRVs in the dependent on the RSC.
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The tcs-offset specifies the start address of the
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TCS in the DRVs.
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- reg-names:
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Usage: required
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Value type: <string>
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Definition: Maps the register specified in the reg property. Must be
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"drv-0", "drv-1", "drv-2" etc and "tcs-offset". The
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- interrupts:
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Usage: required
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Value type: <prop-encoded-interrupt>
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Definition: The interrupt that trips when a message complete/response
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is received for this DRV from the accelerators.
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- qcom,drv-id:
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Usage: required
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Value type: <u32>
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Definition: The id of the DRV in the RSC block that will be used by
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this controller.
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- qcom,tcs-config:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: The tuple defining the configuration of TCS.
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Must have 2 cells which describe each TCS type.
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<type number_of_tcs>.
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The order of the TCS must match the hardware
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configuration.
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- Cell #1 (TCS Type): TCS types to be specified -
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ACTIVE_TCS
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SLEEP_TCS
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WAKE_TCS
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CONTROL_TCS
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- Cell #2 (Number of TCS): <u32>
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- label:
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Usage: optional
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Value type: <string>
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Definition: Name for the RSC. The name would be used in trace logs.
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Drivers that want to use the RSC to communicate with RPMH must specify their
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bindings as child nodes of the RSC controllers they wish to communicate with.
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Example 1:
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For a TCS whose RSC base address is is 0x179C0000 and is at a DRV id of 2, the
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register offsets for DRV2 start at 0D00, the register calculations are like
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this -
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DRV0: 0x179C0000
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DRV2: 0x179C0000 + 0x10000 = 0x179D0000
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DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
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TCS-OFFSET: 0xD00
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apps_rsc: rsc@179c0000 {
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label = "apps_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0x179c0000 0x10000>,
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<0x179d0000 0x10000>,
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<0x179e0000 0x10000>;
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reg-names = "drv-0", "drv-1", "drv-2";
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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qcom,tcs-offset = <0xd00>;
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qcom,drv-id = <2>;
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qcom,tcs-config = <ACTIVE_TCS 2>,
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<SLEEP_TCS 3>,
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<WAKE_TCS 3>,
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<CONTROL_TCS 1>;
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};
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Example 2:
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For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the
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register offsets for DRV0 start at 01C00, the register calculations are like
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this -
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DRV0: 0xAF20000
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TCS-OFFSET: 0x1C00
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disp_rsc: rsc@af20000 {
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label = "disp_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0xaf20000 0x10000>;
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reg-names = "drv-0";
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interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
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qcom,tcs-offset = <0x1c00>;
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qcom,drv-id = <0>;
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qcom,tcs-config = <ACTIVE_TCS 0>,
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<SLEEP_TCS 1>,
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<WAKE_TCS 1>,
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<CONTROL_TCS 0>;
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};
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