QCOM GSBI (General Serial Bus Interface) Driver
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The GSBI controller is modeled as a node with zero or more child nodes, each
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representing a serial sub-node device that is mux'd as part of the GSBI
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configuration settings. The mode setting will govern the input/output mode of
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the 4 GSBI IOs.
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Required properties:
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- compatible: Should contain "qcom,gsbi-v1.0.0"
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- cell-index: Should contain the GSBI index
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- reg: Address range for GSBI registers
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- clocks: required clock
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- clock-names: must contain "iface" entry
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- qcom,mode : indicates MUX value for configuration of the serial interface.
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Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.
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Optional properties:
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- qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
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dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
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- syscon-tcsr: indicates phandle of TCSR syscon node. Required if child uses
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dma.
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Required properties if child node exists:
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- #address-cells: Must be 1
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- #size-cells: Must be 1
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- ranges: Must be present
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Properties for children:
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A GSBI controller node can contain 0 or more child nodes representing serial
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devices. These serial devices can be a QCOM UART, I2C controller, spi
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controller, or some combination of aforementioned devices.
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See the following for child node definitions:
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Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
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Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
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Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
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Example for APQ8064:
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#include <dt-bindings/soc/qcom,gsbi.h>
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gsbi4@16300000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <4>;
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reg = <0x16300000 0x100>;
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clocks = <&gcc GSBI4_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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qcom,mode = <GSBI_PROT_I2C_UART>;
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qcom,crci = <GSBI_CRCI_QUP>;
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syscon-tcsr = <&tcsr>;
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/* child nodes go under here */
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i2c_qup4: i2c@16380000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x16380000 0x1000>;
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interrupts = <0 153 0>;
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clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <200000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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uart4: serial@16340000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16340000 0x1000>,
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<0x16300000 0x1000>;
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interrupts = <0 152 0x0>;
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clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
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clock-names = "core", "iface";
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};
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};
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tcsr: syscon@1a400000 {
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compatible = "qcom,apq8064-tcsr", "syscon";
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reg = <0x1a400000 0x100>;
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};
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