Qualcomm Technologies, Inc. GENI Serial Engine QUP Wrapper Controller
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Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
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is a programmable module for supporting a wide range of serial interfaces
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like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
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Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
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Wrapper controller is modeled as a node with zero or more child nodes each
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representing a serial engine.
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Required properties:
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- compatible: Must be "qcom,geni-se-qup".
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- reg: Must contain QUP register address and length.
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- clock-names: Must contain "m-ahb" and "s-ahb".
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- clocks: AHB clocks needed by the device.
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Required properties if child node exists:
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- #address-cells: Must be <1> for Serial Engine Address
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- #size-cells: Must be <1> for Serial Engine Address Size
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- ranges: Must be present
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Properties for children:
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A GENI based QUP wrapper controller node can contain 0 or more child nodes
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representing serial devices. These serial devices can be a QCOM UART, I2C
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controller, SPI controller, or some combination of aforementioned devices.
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Please refer below the child node definitions for the supported serial
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interface protocols.
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Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller
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Required properties:
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- compatible: Must be "qcom,geni-i2c".
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- reg: Must contain QUP register address and length.
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- interrupts: Must contain I2C interrupt.
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- clock-names: Must contain "se".
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- clocks: Serial engine core clock needed by the device.
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- #address-cells: Must be <1> for I2C device address.
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- #size-cells: Must be <0> as I2C addresses have no size component.
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Optional property:
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- clock-frequency: Desired I2C bus clock frequency in Hz.
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When missing default to 100000Hz.
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Child nodes should conform to I2C bus binding as described in i2c.txt.
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Qualcomm Technologies Inc. GENI Serial Engine based UART Controller
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Required properties:
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- compatible: Must be "qcom,geni-debug-uart" or "qcom,geni-uart".
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- reg: Must contain UART register location and length.
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- interrupts: Must contain UART core interrupts.
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- clock-names: Must contain "se".
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- clocks: Serial engine core clock needed by the device.
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Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller
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Required properties:
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- compatible: Must contain "qcom,geni-spi".
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- reg: Must contain SPI register location and length.
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- interrupts: Must contain SPI controller interrupts.
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- clock-names: Must contain "se".
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- clocks: Serial engine core clock needed by the device.
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- spi-max-frequency: Specifies maximum SPI clock frequency, units - Hz.
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- #address-cells: Must be <1> to define a chip select address on
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the SPI bus.
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- #size-cells: Must be <0>.
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SPI slave nodes must be children of the SPI master node and conform to SPI bus
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binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt.
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Example:
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geniqup@8c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x8c0000 0x6000>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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i2c0: i2c@a94000 {
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compatible = "qcom,geni-i2c";
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reg = <0xa94000 0x4000>;
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interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qup_1_i2c_5_active>;
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pinctrl-1 = <&qup_1_i2c_5_sleep>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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uart0: serial@a88000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0xa88000 0x7000>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qup_1_uart_3_active>;
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pinctrl-1 = <&qup_1_uart_3_sleep>;
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};
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spi0: spi@a84000 {
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compatible = "qcom,geni-spi";
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reg = <0xa84000 0x4000>;
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interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qup_1_spi_2_active>;
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pinctrl-1 = <&qup_1_spi_2_sleep>;
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spi-max-frequency = <19200000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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}
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