MIPS CPU interrupt controller
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On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU
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IRQs from a devicetree file and create a irq_domain for IRQ controller.
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With the irq_domain in place we can describe how the 8 IRQs are wired to the
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platforms internal interrupt controller cascade.
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Below is an example of a platform describing the cascade inside the devicetree
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and the code used to load it inside arch_init_irq().
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Required properties:
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- compatible : Should be "mti,cpu-interrupt-controller"
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Example devicetree:
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cpu-irq: cpu-irq {
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#address-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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compatible = "mti,cpu-interrupt-controller";
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};
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intc: intc@200 {
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compatible = "ralink,rt2880-intc";
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reg = <0x200 0x100>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpu-irq>;
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interrupts = <2>;
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};
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Example platform irq.c:
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static struct of_device_id __initdata of_irq_ids[] = {
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{ .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
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{ .compatible = "ralink,rt2880-intc", .data = intc_of_init },
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{},
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};
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void __init arch_init_irq(void)
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{
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of_irq_init(of_irq_ids);
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}
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