* Boot Bus
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The Octeon Boot Bus is a configurable parallel bus with 8 chip
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selects. Each chip select is independently configurable.
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Properties:
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- compatible: "cavium,octeon-3860-bootbus"
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Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
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- reg: The base address of the Boot Bus' register bank.
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- #address-cells: Must be <2>. The first cell is the chip select
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within the bootbus. The second cell is the offset from the chip select.
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- #size-cells: Must be <1>.
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- ranges: There must be one one triplet of (child-bus-address,
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parent-bus-address, length) for each active chip select. If the
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length element for any triplet is zero, the chip select is disabled,
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making it inactive.
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The configuration parameters for each chip select are stored in child
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nodes.
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Configuration Properties:
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- compatible: "cavium,octeon-3860-bootbus-config"
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- cavium,cs-index: A single cell indicating the chip select that
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corresponds to this configuration.
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- cavium,t-adr: A cell specifying the ADR timing (in nS).
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- cavium,t-ce: A cell specifying the CE timing (in nS).
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- cavium,t-oe: A cell specifying the OE timing (in nS).
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- cavium,t-we: A cell specifying the WE timing (in nS).
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- cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
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- cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
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- cavium,t-pause: A cell specifying the PAUSE timing (in nS).
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- cavium,t-wait: A cell specifying the WAIT timing (in nS).
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- cavium,t-page: A cell specifying the PAGE timing (in nS).
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- cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
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- cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1
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= 2 bytes, 2 = 4 bytes, 3 = 8 bytes).
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- cavium,wait-mode: Optional. If present, wait mode (WAITM) is selected.
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- cavium,page-mode: Optional. If present, page mode (PAGEM) is selected.
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- cavium,bus-width: A cell specifying the WIDTH parameter (in bits) of
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the bus for this chip select.
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- cavium,ale-mode: Optional. If present, ALE mode is selected.
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- cavium,sam-mode: Optional. If present, SAM mode is selected.
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- cavium,or-mode: Optional. If present, OR mode is selected.
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Example:
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bootbus: bootbus@1180000000000 {
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compatible = "cavium,octeon-3860-bootbus";
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reg = <0x11800 0x00000000 0x0 0x200>;
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/* The chip select number and offset */
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#address-cells = <2>;
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/* The size of the chip select region */
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#size-cells = <1>;
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ranges = <0 0 0x0 0x1f400000 0xc00000>,
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<1 0 0x10000 0x30000000 0>,
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<2 0 0x10000 0x40000000 0>,
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<3 0 0x10000 0x50000000 0>,
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<4 0 0x0 0x1d020000 0x10000>,
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<5 0 0x0 0x1d040000 0x10000>,
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<6 0 0x0 0x1d050000 0x10000>,
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<7 0 0x10000 0x90000000 0>;
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cavium,cs-config@0 {
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compatible = "cavium,octeon-3860-bootbus-config";
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cavium,cs-index = <0>;
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cavium,t-adr = <20>;
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cavium,t-ce = <60>;
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cavium,t-oe = <60>;
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cavium,t-we = <45>;
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cavium,t-rd-hld = <35>;
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cavium,t-wr-hld = <45>;
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cavium,t-pause = <0>;
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cavium,t-wait = <0>;
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cavium,t-page = <35>;
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cavium,t-rd-dly = <0>;
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cavium,pages = <0>;
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cavium,bus-width = <8>;
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};
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.
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.
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.
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cavium,cs-config@6 {
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compatible = "cavium,octeon-3860-bootbus-config";
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cavium,cs-index = <6>;
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cavium,t-adr = <5>;
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cavium,t-ce = <300>;
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cavium,t-oe = <270>;
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cavium,t-we = <150>;
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cavium,t-rd-hld = <100>;
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cavium,t-wr-hld = <70>;
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cavium,t-pause = <0>;
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cavium,t-wait = <0>;
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cavium,t-page = <320>;
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cavium,t-rd-dly = <0>;
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cavium,pages = <0>;
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cavium,wait-mode;
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cavium,bus-width = <16>;
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};
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.
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.
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.
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};
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