DT bindings for Xilinx video IP cores
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Xilinx video IP cores process video streams by acting as video sinks and/or
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sources. They are connected by links through their input and output ports,
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creating a video pipeline.
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Each video IP core is represented by an AMBA bus child node in the device
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tree using bindings documented in this directory. Connections between the IP
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cores are represented as defined in ../video-interfaces.txt.
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The whole pipeline is represented by an AMBA bus child node in the device
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tree using bindings documented in ./xlnx,video.txt.
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Common properties
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-----------------
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The following properties are common to all Xilinx video IP cores.
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- xlnx,video-format: This property represents a video format transmitted on an
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AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
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Video IP and System Design Guide" [UG934]. How the format relates to the IP
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core is described in the IP core bindings documentation.
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- xlnx,video-width: This property qualifies the video format with the sample
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width expressed as a number of bits per pixel component. All components must
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use the same width.
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- xlnx,cfa-pattern: When the video format is set to Mono/Sensor, this property
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describes the sensor's color filter array pattern. Supported values are
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"bggr", "gbrg", "grbg", "rggb" and "mono". If not specified, the pattern
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defaults to "mono".
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[UG934] http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf
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