Binding for TI mux clock.
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Binding status: Unstable - ABI compatibility may be broken in the future
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This binding uses the common clock binding[1]. It assumes a
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register-mapped multiplexer with multiple input clock signals or
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parents, one of which can be selected as output. This clock does not
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gate or adjust the parent rate via a divider or multiplier.
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By default the "clocks" property lists the parents in the same order
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as they are programmed into the regster. E.g:
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clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
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results in programming the register as follows:
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register value selected parent clock
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0 foo_clock
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1 bar_clock
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2 baz_clock
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Some clock controller IPs do not allow a value of zero to be programmed
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into the register, instead indexing begins at 1. The optional property
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"index-starts-at-one" modified the scheme as follows:
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register value selected clock parent
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1 foo_clock
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2 bar_clock
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3 baz_clock
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The binding must provide the register to control the mux. Optionally
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the number of bits to shift the control field in the register can be
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supplied. If the shift value is missing it is the same as supplying
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a zero shift.
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
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- #clock-cells : from common clock binding; shall be set to 0.
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- clocks : link phandles of parent clocks
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- reg : register offset for register controlling adjustable mux
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Optional properties:
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- ti,bit-shift : number of bits to shift the bit-mask, defaults to
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0 if not present
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- ti,index-starts-at-one : valid input select programming starts at 1, not
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zero
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- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
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not supported by the composite-mux-clock subtype
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- ti,latch-bit : latch the mux value to HW, only needed if the register
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access requires this. As an example, dra7x DPLL_GMAC H14 muxing
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implements such behavior.
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Examples:
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sys_clkin_ck: sys_clkin_ck@4a306110 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
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reg = <0x0110>;
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ti,index-starts-at-one;
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};
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abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
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ti,bit-shift = <24>;
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reg = <0x0108>;
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};
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mcbsp5_mux_fck: mcbsp5_mux_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&core_96m_fck>, <&mcbsp_clks>;
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ti,bit-shift = <4>;
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reg = <0x02d8>;
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};
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