Binding for Texas Instruments gate clock.
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Binding status: Unstable - ABI compatibility may be broken in the future
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This binding uses the common clock binding[1]. This clock is
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quite much similar to the basic gate-clock [2], however,
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it supports a number of additional features. If no register
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is provided for this clock, the code assumes that a clockdomain
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will be controlled instead and the corresponding hw-ops for
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that is used.
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
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[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
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Required properties:
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- compatible : shall be one of:
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"ti,gate-clock" - basic gate clock
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"ti,wait-gate-clock" - gate clock which waits until clock is active before
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returning from clk_enable()
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"ti,dss-gate-clock" - gate clock with DSS specific hardware handling
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"ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
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"ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
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clock directly from a clockdomain, see [3] how
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to map clockdomains properly
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"ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
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required for a hardware errata
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"ti,composite-gate-clock" - composite gate clock, to be part of composite
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clock
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"ti,composite-no-wait-gate-clock" - composite gate clock that does not wait
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for clock to be active before returning
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from clk_enable()
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- #clock-cells : from common clock binding; shall be set to 0
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- clocks : link to phandle of parent clock
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- reg : offset for register controlling adjustable gate, not needed for
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ti,clkdm-gate-clock type
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Optional properties:
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- ti,bit-shift : bit shift for programming the clock gate, invalid for
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ti,clkdm-gate-clock type
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- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
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gates the clock and clearing the bit ungates the clock.
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Examples:
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mmchs2_fck: mmchs2_fck@48004a00 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&core_96m_fck>;
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reg = <0x0a00>;
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ti,bit-shift = <25>;
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};
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uart4_fck_am35xx: uart4_fck_am35xx {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&core_48m_fck>;
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reg = <0x0a00>;
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ti,bit-shift = <23>;
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};
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dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
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#clock-cells = <0>;
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compatible = "ti,dss-gate-clock";
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clocks = <&dpll4_m4x2_ck>;
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reg = <0x0e00>;
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ti,bit-shift = <0>;
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};
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emac_ick: emac_ick@4800259c {
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#clock-cells = <0>;
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compatible = "ti,am35xx-gate-clock";
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clocks = <&ipss_ick>;
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reg = <0x059c>;
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ti,bit-shift = <1>;
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};
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emu_src_ck: emu_src_ck {
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#clock-cells = <0>;
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compatible = "ti,clkdm-gate-clock";
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clocks = <&emu_src_mux_ck>;
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};
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dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
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#clock-cells = <0>;
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compatible = "ti,hsdiv-gate-clock";
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clocks = <&dpll4_m2x2_mul_ck>;
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ti,bit-shift = <0x1b>;
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reg = <0x0d00>;
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ti,set-bit-to-disable;
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};
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vlynq_gate_fck: vlynq_gate_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-gate-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <3>;
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reg = <0x0200>;
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};
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sys_clkout2_src_gate: sys_clkout2_src_gate {
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#clock-cells = <0>;
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compatible = "ti,composite-no-wait-gate-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <15>;
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reg = <0x0070>;
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};
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