Binding for TI divider clock
|
|
Binding status: Unstable - ABI compatibility may be broken in the future
|
|
This binding uses the common clock binding[1]. It assumes a
|
register-mapped adjustable clock rate divider that does not gate and has
|
only one input clock or parent. By default the value programmed into
|
the register is one less than the actual divisor value. E.g:
|
|
register value actual divisor value
|
0 1
|
1 2
|
2 3
|
|
This assumption may be modified by the following optional properties:
|
|
ti,index-starts-at-one - valid divisor values start at 1, not the default
|
of 0. E.g:
|
register value actual divisor value
|
1 1
|
2 2
|
3 3
|
|
ti,index-power-of-two - valid divisor values are powers of two. E.g:
|
register value actual divisor value
|
0 1
|
1 2
|
2 4
|
|
Additionally an array of valid dividers may be supplied like so:
|
|
ti,dividers = <4>, <8>, <0>, <16>;
|
|
Which will map the resulting values to a divisor table by their index:
|
register value actual divisor value
|
0 4
|
1 8
|
2 <invalid divisor, skipped>
|
3 16
|
|
Any zero value in this array means the corresponding bit-value is invalid
|
and must not be used.
|
|
The binding must also provide the register to control the divider and
|
unless the divider array is provided, min and max dividers. Optionally
|
the number of bits to shift that mask, if necessary. If the shift value
|
is missing it is the same as supplying a zero shift.
|
|
This binding can also optionally provide support to the hardware autoidle
|
feature, see [2].
|
|
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
|
|
Required properties:
|
- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
|
- #clock-cells : from common clock binding; shall be set to 0.
|
- clocks : link to phandle of parent clock
|
- reg : offset for register controlling adjustable divider
|
|
Optional properties:
|
- clock-output-names : from common clock binding.
|
- ti,dividers : array of integers defining divisors
|
- ti,bit-shift : number of bits to shift the divider value, defaults to 0
|
- ti,min-div : min divisor for dividing the input clock rate, only
|
needed if the first divisor is offset from the default value (1)
|
- ti,max-div : max divisor for dividing the input clock rate, only needed
|
if ti,dividers is not defined.
|
- ti,index-starts-at-one : valid divisor programming starts at 1, not zero,
|
only valid if ti,dividers is not defined.
|
- ti,index-power-of-two : valid divisor programming must be a power of two,
|
only valid if ti,dividers is not defined.
|
- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,
|
see [2]
|
- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
|
see [2]
|
- ti,set-rate-parent : clk_set_rate is propagated to parent
|
- ti,latch-bit : latch the divider value to HW, only needed if the register
|
access requires this. As an example dra76x DPLL_GMAC H14 divider implements
|
such behavior.
|
|
Examples:
|
dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
|
#clock-cells = <0>;
|
compatible = "ti,divider-clock";
|
clocks = <&dpll_usb_ck>;
|
ti,max-div = <127>;
|
reg = <0x190>;
|
ti,index-starts-at-one;
|
};
|
|
aess_fclk: aess_fclk@4a004528 {
|
#clock-cells = <0>;
|
compatible = "ti,divider-clock";
|
clocks = <&abe_clk>;
|
ti,bit-shift = <24>;
|
reg = <0x528>;
|
ti,max-div = <2>;
|
};
|
|
dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
|
#clock-cells = <0>;
|
compatible = "ti,composite-divider-clock";
|
clocks = <&dpll_core_x2_ck>;
|
ti,max-div = <31>;
|
reg = <0x0134>;
|
ti,index-starts-at-one;
|
};
|
|
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
|
#clock-cells = <0>;
|
compatible = "ti,composite-divider-clock";
|
clocks = <&corex2_fck>;
|
ti,bit-shift = <8>;
|
reg = <0x0a40>;
|
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
|
};
|
