// SPDX-License-Identifier: GPL-2.0
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2016 Realtek Corporation.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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/* ************************************************************
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* include files
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* *************************************************************/
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#include "mp_precomp.h"
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#include "phydm_precomp.h"
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#include "phydm_noisemonitor.h"
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/* *************************************************
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* This function is for inband noise test utility only
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* To obtain the inband noise level(dbm), do the following.
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* 1. disable DIG and Power Saving
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* 2. Set initial gain = 0x1a
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* 3. Stop updating idle time pwer report (for driver read)
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* - 0x80c[25]
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*
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* **************************************************/
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#define VALID_MIN -35
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#define VALID_MAX 10
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#define VALID_CNT 5
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static inline void phydm_set_noise_data_sum(struct noise_level *noise_data,
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u8 max_rf_path)
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{
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u8 rf_path;
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for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) {
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if (noise_data->valid_cnt[rf_path])
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noise_data->sum[rf_path] /=
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noise_data->valid_cnt[rf_path];
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else
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noise_data->sum[rf_path] = 0;
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}
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}
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static s16 odm_inband_noise_monitor_n_series(struct phy_dm_struct *dm,
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u8 is_pause_dig, u8 igi_value,
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u32 max_time)
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{
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u32 tmp4b;
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u8 max_rf_path = 0, rf_path;
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u8 reg_c50, reg_c58, valid_done = 0;
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struct noise_level noise_data;
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u64 start = 0, func_start = 0, func_end = 0;
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func_start = odm_get_current_time(dm);
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dm->noise_level.noise_all = 0;
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if ((dm->rf_type == ODM_1T2R) || (dm->rf_type == ODM_2T2R))
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max_rf_path = 2;
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else
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max_rf_path = 1;
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ODM_RT_TRACE(dm, ODM_COMP_COMMON, "%s() ==>\n", __func__);
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odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));
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/* */
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/* step 1. Disable DIG && Set initial gain. */
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/* */
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if (is_pause_dig)
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odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value);
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/* */
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/* step 2. Disable all power save for read registers */
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/* */
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/* dcmd_DebugControlPowerSave(adapter, PSDisable); */
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/* */
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/* step 3. Get noise power level */
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/* */
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start = odm_get_current_time(dm);
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while (1) {
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/* Stop updating idle time pwer report (for driver read) */
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odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1);
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/* Read Noise Floor Report */
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tmp4b = odm_get_bb_reg(dm, 0x8f8, MASKDWORD);
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ODM_RT_TRACE(dm, ODM_COMP_COMMON,
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"Noise Floor Report (0x8f8) = 0x%08x\n", tmp4b);
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/* update idle time pwer report per 5us */
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odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0);
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noise_data.value[ODM_RF_PATH_A] = (u8)(tmp4b & 0xff);
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noise_data.value[ODM_RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
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ODM_RT_TRACE(dm, ODM_COMP_COMMON,
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"value_a = 0x%x(%d), value_b = 0x%x(%d)\n",
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noise_data.value[ODM_RF_PATH_A],
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noise_data.value[ODM_RF_PATH_A],
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noise_data.value[ODM_RF_PATH_B],
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noise_data.value[ODM_RF_PATH_B]);
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for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path;
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rf_path++) {
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noise_data.sval[rf_path] =
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(s8)noise_data.value[rf_path];
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noise_data.sval[rf_path] /= 2;
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}
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ODM_RT_TRACE(dm, ODM_COMP_COMMON, "sval_a = %d, sval_b = %d\n",
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noise_data.sval[ODM_RF_PATH_A],
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noise_data.sval[ODM_RF_PATH_B]);
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for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path;
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rf_path++) {
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if (!(noise_data.valid_cnt[rf_path] < VALID_CNT) ||
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!(noise_data.sval[rf_path] < VALID_MAX &&
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noise_data.sval[rf_path] >= VALID_MIN)) {
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continue;
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}
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noise_data.valid_cnt[rf_path]++;
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noise_data.sum[rf_path] += noise_data.sval[rf_path];
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ODM_RT_TRACE(dm, ODM_COMP_COMMON,
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"rf_path:%d Valid sval = %d\n", rf_path,
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noise_data.sval[rf_path]);
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ODM_RT_TRACE(dm, ODM_COMP_COMMON, "Sum of sval = %d,\n",
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noise_data.sum[rf_path]);
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if (noise_data.valid_cnt[rf_path] == VALID_CNT) {
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valid_done++;
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ODM_RT_TRACE(
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dm, ODM_COMP_COMMON,
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"After divided, rf_path:%d,sum = %d\n",
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rf_path, noise_data.sum[rf_path]);
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}
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}
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if ((valid_done == max_rf_path) ||
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(odm_get_progressing_time(dm, start) > max_time)) {
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phydm_set_noise_data_sum(&noise_data, max_rf_path);
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break;
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}
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}
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reg_c50 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0);
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reg_c50 &= ~BIT(7);
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ODM_RT_TRACE(dm, ODM_COMP_COMMON, "0x%x = 0x%02x(%d)\n",
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REG_OFDM_0_XA_AGC_CORE1, reg_c50, reg_c50);
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dm->noise_level.noise[ODM_RF_PATH_A] =
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(u8)(-110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]);
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dm->noise_level.noise_all += dm->noise_level.noise[ODM_RF_PATH_A];
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if (max_rf_path == 2) {
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reg_c58 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XB_AGC_CORE1,
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MASKBYTE0);
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reg_c58 &= ~BIT(7);
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ODM_RT_TRACE(dm, ODM_COMP_COMMON, "0x%x = 0x%02x(%d)\n",
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REG_OFDM_0_XB_AGC_CORE1, reg_c58, reg_c58);
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dm->noise_level.noise[ODM_RF_PATH_B] =
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(u8)(-110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B]);
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dm->noise_level.noise_all +=
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dm->noise_level.noise[ODM_RF_PATH_B];
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}
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dm->noise_level.noise_all /= max_rf_path;
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ODM_RT_TRACE(dm, ODM_COMP_COMMON, "noise_a = %d, noise_b = %d\n",
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dm->noise_level.noise[ODM_RF_PATH_A],
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dm->noise_level.noise[ODM_RF_PATH_B]);
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/* */
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/* step 4. Recover the Dig */
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/* */
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if (is_pause_dig)
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odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value);
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func_end = odm_get_progressing_time(dm, func_start);
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ODM_RT_TRACE(dm, ODM_COMP_COMMON, "%s() <==\n", __func__);
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return dm->noise_level.noise_all;
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}
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static s16 odm_inband_noise_monitor_ac_series(struct phy_dm_struct *dm,
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u8 is_pause_dig, u8 igi_value,
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u32 max_time)
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{
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s32 rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/
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s32 value32, pwdb_A = 0, sval, noise, sum;
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bool pd_flag;
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u8 valid_cnt;
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u64 start = 0, func_start = 0, func_end = 0;
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if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A)))
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return 0;
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func_start = odm_get_current_time(dm);
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dm->noise_level.noise_all = 0;
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ODM_RT_TRACE(dm, ODM_COMP_COMMON, "%s() ==>\n", __func__);
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/* step 1. Disable DIG && Set initial gain. */
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if (is_pause_dig)
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odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value);
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/* step 2. Disable all power save for read registers */
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/*dcmd_DebugControlPowerSave(adapter, PSDisable); */
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/* step 3. Get noise power level */
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start = odm_get_current_time(dm);
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/* reset counters */
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sum = 0;
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valid_cnt = 0;
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/* step 3. Get noise power level */
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while (1) {
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/*Set IGI=0x1C */
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odm_write_dig(dm, 0x1C);
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/*stop CK320&CK88 */
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odm_set_bb_reg(dm, 0x8B4, BIT(6), 1);
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/*Read path-A */
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odm_set_bb_reg(dm, 0x8FC, MASKDWORD, 0x200); /*set debug port*/
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value32 = odm_get_bb_reg(dm, 0xFA0,
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MASKDWORD); /*read debug port*/
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rxi_buf_anta = (value32 & 0xFFC00) >>
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10; /*rxi_buf_anta=RegFA0[19:10]*/
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rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/
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pd_flag = (bool)((value32 & BIT(31)) >> 31);
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/*Not in packet detection period or Tx state */
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if ((!pd_flag) || (rxi_buf_anta != 0x200)) {
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/*sign conversion*/
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rxi_buf_anta = odm_sign_conversion(rxi_buf_anta, 10);
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rxq_buf_anta = odm_sign_conversion(rxq_buf_anta, 10);
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pwdb_A = odm_pwdb_conversion(
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rxi_buf_anta * rxi_buf_anta +
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rxq_buf_anta * rxq_buf_anta,
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20, 18); /*S(10,9)*S(10,9)=S(20,18)*/
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ODM_RT_TRACE(
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dm, ODM_COMP_COMMON,
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"pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n",
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pwdb_A, rxi_buf_anta & 0x3FF,
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rxq_buf_anta & 0x3FF);
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}
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/*Start CK320&CK88*/
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odm_set_bb_reg(dm, 0x8B4, BIT(6), 0);
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/*BB Reset*/
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odm_write_1byte(dm, 0x02, odm_read_1byte(dm, 0x02) & (~BIT(0)));
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odm_write_1byte(dm, 0x02, odm_read_1byte(dm, 0x02) | BIT(0));
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/*PMAC Reset*/
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odm_write_1byte(dm, 0xB03,
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odm_read_1byte(dm, 0xB03) & (~BIT(0)));
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odm_write_1byte(dm, 0xB03, odm_read_1byte(dm, 0xB03) | BIT(0));
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/*CCK Reset*/
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if (odm_read_1byte(dm, 0x80B) & BIT(4)) {
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odm_write_1byte(dm, 0x80B,
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odm_read_1byte(dm, 0x80B) & (~BIT(4)));
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odm_write_1byte(dm, 0x80B,
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odm_read_1byte(dm, 0x80B) | BIT(4));
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}
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sval = pwdb_A;
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if ((sval < 0 && sval >= -27) && (valid_cnt < VALID_CNT)) {
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valid_cnt++;
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sum += sval;
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ODM_RT_TRACE(dm, ODM_COMP_COMMON, "Valid sval = %d\n",
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sval);
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ODM_RT_TRACE(dm, ODM_COMP_COMMON, "Sum of sval = %d,\n",
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sum);
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if ((valid_cnt >= VALID_CNT) ||
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(odm_get_progressing_time(dm, start) > max_time)) {
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sum /= VALID_CNT;
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ODM_RT_TRACE(dm, ODM_COMP_COMMON,
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"After divided, sum = %d\n", sum);
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break;
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}
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}
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}
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/*ADC backoff is 12dB,*/
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/*Ptarget=0x1C-110=-82dBm*/
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noise = sum + 12 + 0x1C - 110;
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/*Offset*/
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noise = noise - 3;
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ODM_RT_TRACE(dm, ODM_COMP_COMMON, "noise = %d\n", noise);
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dm->noise_level.noise_all = (s16)noise;
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/* step 4. Recover the Dig*/
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if (is_pause_dig)
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odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value);
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func_end = odm_get_progressing_time(dm, func_start);
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ODM_RT_TRACE(dm, ODM_COMP_COMMON, "%s() <==\n", __func__);
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return dm->noise_level.noise_all;
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}
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s16 odm_inband_noise_monitor(void *dm_void, u8 is_pause_dig, u8 igi_value,
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u32 max_time)
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{
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struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
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if (dm->support_ic_type & ODM_IC_11AC_SERIES)
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return odm_inband_noise_monitor_ac_series(dm, is_pause_dig,
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igi_value, max_time);
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else
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return odm_inband_noise_monitor_n_series(dm, is_pause_dig,
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igi_value, max_time);
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}
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