/* SPDX-License-Identifier: GPL-2.0 */
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2016 Realtek Corporation.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __ODM_INTERFACE_H__
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#define __ODM_INTERFACE_H__
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#define INTERFACE_VERSION "1.1" /*2015.07.29 YuChen*/
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/*
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* =========== Constant/Structure/Enum/... Define
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*/
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/*
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* =========== Macro Define
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*/
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#define _reg_all(_name) ODM_##_name
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#define _reg_ic(_name, _ic) ODM_##_name##_ic
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#define _bit_all(_name) BIT_##_name
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#define _bit_ic(_name, _ic) BIT_##_name##_ic
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/* _cat: implemented by Token-Pasting Operator. */
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/*===================================
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*
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* #define ODM_REG_DIG_11N 0xC50
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* #define ODM_REG_DIG_11AC 0xDDD
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*
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* ODM_REG(DIG,_pdm_odm)
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* ===================================
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*/
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#define _reg_11N(_name) ODM_REG_##_name##_11N
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#define _reg_11AC(_name) ODM_REG_##_name##_11AC
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#define _bit_11N(_name) ODM_BIT_##_name##_11N
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#define _bit_11AC(_name) ODM_BIT_##_name##_11AC
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#define _cat(_name, _ic_type, _func) \
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(((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
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_func##_11AC(_name))
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/* _name: name of register or bit.
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* Example: "ODM_REG(R_A_AGC_CORE1, dm)"
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* gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C",
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* depends on support_ic_type.
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*/
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#define ODM_REG(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _reg)
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#define ODM_BIT(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _bit)
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enum phydm_h2c_cmd {
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PHYDM_H2C_TXBF = 0x41,
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ODM_H2C_RSSI_REPORT = 0x42,
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ODM_H2C_IQ_CALIBRATION = 0x45,
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ODM_H2C_RA_PARA_ADJUST = 0x47,
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PHYDM_H2C_DYNAMIC_TX_PATH = 0x48,
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PHYDM_H2C_FW_TRACE_EN = 0x49,
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ODM_H2C_WIFI_CALIBRATION = 0x6d,
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PHYDM_H2C_MU = 0x4a,
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ODM_MAX_H2CCMD
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};
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enum phydm_c2h_evt {
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PHYDM_C2H_DBG = 0,
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PHYDM_C2H_LB = 1,
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PHYDM_C2H_XBF = 2,
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PHYDM_C2H_TX_REPORT = 3,
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PHYDM_C2H_INFO = 9,
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PHYDM_C2H_BT_MP = 11,
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PHYDM_C2H_RA_RPT = 12,
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PHYDM_C2H_RA_PARA_RPT = 14,
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PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15,
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PHYDM_C2H_IQK_FINISH = 17, /*0x11*/
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PHYDM_C2H_DBG_CODE = 0xFE,
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PHYDM_C2H_EXTEND = 0xFF,
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};
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enum phydm_extend_c2h_evt {
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PHYDM_EXTEND_C2H_DBG_PRINT = 0
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};
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/*
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* =========== Extern Variable ??? It should be forbidden.
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*/
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/*
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* =========== EXtern Function Prototype
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*/
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u8 odm_read_1byte(struct phy_dm_struct *dm, u32 reg_addr);
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u16 odm_read_2byte(struct phy_dm_struct *dm, u32 reg_addr);
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u32 odm_read_4byte(struct phy_dm_struct *dm, u32 reg_addr);
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void odm_write_1byte(struct phy_dm_struct *dm, u32 reg_addr, u8 data);
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void odm_write_2byte(struct phy_dm_struct *dm, u32 reg_addr, u16 data);
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void odm_write_4byte(struct phy_dm_struct *dm, u32 reg_addr, u32 data);
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void odm_set_mac_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask,
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u32 data);
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u32 odm_get_mac_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask);
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void odm_set_bb_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask,
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u32 data);
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u32 odm_get_bb_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask);
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void odm_set_rf_reg(struct phy_dm_struct *dm, enum odm_rf_radio_path e_rf_path,
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u32 reg_addr, u32 bit_mask, u32 data);
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u32 odm_get_rf_reg(struct phy_dm_struct *dm, enum odm_rf_radio_path e_rf_path,
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u32 reg_addr, u32 bit_mask);
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/*
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* Memory Relative Function.
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*/
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void odm_allocate_memory(struct phy_dm_struct *dm, void **ptr, u32 length);
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void odm_free_memory(struct phy_dm_struct *dm, void *ptr, u32 length);
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void odm_move_memory(struct phy_dm_struct *dm, void *p_dest, void *src,
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u32 length);
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s32 odm_compare_memory(struct phy_dm_struct *dm, void *p_buf1, void *buf2,
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u32 length);
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void odm_memory_set(struct phy_dm_struct *dm, void *pbuf, s8 value, u32 length);
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/*
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* ODM MISC-spin lock relative API.
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*/
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void odm_acquire_spin_lock(struct phy_dm_struct *dm,
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enum rt_spinlock_type type);
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void odm_release_spin_lock(struct phy_dm_struct *dm,
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enum rt_spinlock_type type);
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/*
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* ODM Timer relative API.
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*/
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void odm_stall_execution(u32 us_delay);
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void ODM_delay_ms(u32 ms);
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void ODM_delay_us(u32 us);
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void ODM_sleep_ms(u32 ms);
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void ODM_sleep_us(u32 us);
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/*
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* ODM FW relative API.
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*/
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void odm_fill_h2c_cmd(struct phy_dm_struct *dm, u8 element_id, u32 cmd_len,
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u8 *cmd_buffer);
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u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len,
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u8 *tmp_buf);
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u64 odm_get_current_time(struct phy_dm_struct *dm);
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u64 odm_get_progressing_time(struct phy_dm_struct *dm, u64 start_time);
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void odm_set_tx_power_index_by_rate_section(struct phy_dm_struct *dm,
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u8 rf_path, u8 channel,
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u8 rate_section);
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u8 odm_get_tx_power_index(struct phy_dm_struct *dm, u8 rf_path, u8 tx_rate,
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u8 band_width, u8 channel);
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#endif /* __ODM_INTERFACE_H__ */
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