/* SPDX-License-Identifier: GPL-2.0 */
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2016 Realtek Corporation.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __ODM_DBG_H__
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#define __ODM_DBG_H__
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/*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/
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/*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/
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#define DEBUG_VERSION "1.3" /*2016.04.28 YuChen*/
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#define ODM_DBG_TRACE 5
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/*FW DBG MSG*/
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#define RATE_DECISION BIT(0)
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#define INIT_RA_TABLE BIT(1)
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#define RATE_UP BIT(2)
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#define RATE_DOWN BIT(3)
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#define TRY_DONE BIT(4)
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#define RA_H2C BIT(5)
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#define F_RATE_AP_RPT BIT(7)
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/* -----------------------------------------------------------------------------
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* Define the tracing components
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*
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* -----------------------------------------------------------------------------
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*/
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/*BB FW Functions*/
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#define PHYDM_FW_COMP_RA BIT(0)
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#define PHYDM_FW_COMP_MU BIT(1)
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#define PHYDM_FW_COMP_PATH_DIV BIT(2)
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#define PHYDM_FW_COMP_PHY_CONFIG BIT(3)
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/*BB Driver Functions*/
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#define ODM_COMP_DIG BIT(0)
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#define ODM_COMP_RA_MASK BIT(1)
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#define ODM_COMP_DYNAMIC_TXPWR BIT(2)
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#define ODM_COMP_FA_CNT BIT(3)
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#define ODM_COMP_RSSI_MONITOR BIT(4)
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#define ODM_COMP_SNIFFER BIT(5)
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#define ODM_COMP_ANT_DIV BIT(6)
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#define ODM_COMP_DFS BIT(7)
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#define ODM_COMP_NOISY_DETECT BIT(8)
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#define ODM_COMP_RATE_ADAPTIVE BIT(9)
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#define ODM_COMP_PATH_DIV BIT(10)
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#define ODM_COMP_CCX BIT(11)
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#define ODM_COMP_DYNAMIC_PRICCA BIT(12)
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/*BIT13 TBD*/
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#define ODM_COMP_MP BIT(14)
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#define ODM_COMP_CFO_TRACKING BIT(15)
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#define ODM_COMP_ACS BIT(16)
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#define PHYDM_COMP_ADAPTIVITY BIT(17)
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#define PHYDM_COMP_RA_DBG BIT(18)
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#define PHYDM_COMP_TXBF BIT(19)
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/* MAC Functions */
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#define ODM_COMP_EDCA_TURBO BIT(20)
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#define ODM_COMP_DYNAMIC_RX_PATH BIT(21)
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#define ODM_FW_DEBUG_TRACE BIT(22)
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/* RF Functions */
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/*BIT23 TBD*/
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#define ODM_COMP_TX_PWR_TRACK BIT(24)
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/*BIT25 TBD*/
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#define ODM_COMP_CALIBRATION BIT(26)
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/* Common Functions */
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/*BIT27 TBD*/
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#define ODM_PHY_CONFIG BIT(28)
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#define ODM_COMP_INIT BIT(29)
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#define ODM_COMP_COMMON BIT(30)
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#define ODM_COMP_API BIT(31)
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#define ODM_COMP_UNCOND 0xFFFFFFFF
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/*------------------------Export Marco Definition---------------------------*/
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#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA)
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#define ODM_RT_TRACE(dm, comp, fmt, ...) \
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do { \
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if (((comp) & dm->debug_components) || \
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((comp) == ODM_COMP_UNCOND)) \
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RT_TRACE(dm->adapter, COMP_PHYDM, DBG_DMESG, fmt, \
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##__VA_ARGS__); \
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} while (0)
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#define BB_DBGPORT_PRIORITY_3 3 /*Debug function (the highest priority)*/
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#define BB_DBGPORT_PRIORITY_2 2 /*Check hang function & Strong function*/
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#define BB_DBGPORT_PRIORITY_1 1 /*Watch dog function*/
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#define BB_DBGPORT_RELEASE 0 /*Init value (the lowest priority)*/
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void phydm_init_debug_setting(struct phy_dm_struct *dm);
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u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port);
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void phydm_release_bb_dbg_port(void *dm_void);
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u32 phydm_get_bb_dbg_port_value(void *dm_void);
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void phydm_basic_dbg_message(void *dm_void);
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#define PHYDM_DBGPRINT 0
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#define MAX_ARGC 20
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#define MAX_ARGV 16
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#define DCMD_DECIMAL "%d"
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#define DCMD_CHAR "%c"
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#define DCMD_HEX "%x"
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#define PHYDM_SSCANF(x, y, z) \
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do { \
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if (sscanf(x, y, z) != 1) \
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ODM_RT_TRACE(dm, ODM_COMP_UNCOND, \
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"%s:%d sscanf fail!", __func__, \
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__LINE__); \
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} while (0)
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#define PHYDM_VAST_INFO_SNPRINTF(msg, ...) \
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do { \
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snprintf(msg, ##__VA_ARGS__); \
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ODM_RT_TRACE(dm, ODM_COMP_UNCOND, output); \
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} while (0)
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#if (PHYDM_DBGPRINT == 1)
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#define PHYDM_SNPRINTF(msg, ...) \
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do { \
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snprintf(msg, ##__VA_ARGS__); \
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ODM_RT_TRACE(dm, ODM_COMP_UNCOND, output); \
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} while (0)
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#else
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#define PHYDM_SNPRINTF(msg, ...) \
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do { \
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if (out_len > used) \
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used += snprintf(msg, ##__VA_ARGS__); \
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} while (0)
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#endif
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void phydm_basic_profile(void *dm_void, u32 *_used, char *output,
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u32 *_out_len);
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s32 phydm_cmd(struct phy_dm_struct *dm, char *input, u32 in_len, u8 flag,
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char *output, u32 out_len);
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void phydm_cmd_parser(struct phy_dm_struct *dm, char input[][16], u32 input_num,
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u8 flag, char *output, u32 out_len);
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bool phydm_api_trx_mode(struct phy_dm_struct *dm, enum odm_rf_path tx_path,
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enum odm_rf_path rx_path, bool is_tx2_path);
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void phydm_fw_trace_en_h2c(void *dm_void, bool enable, u32 fw_debug_component,
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u32 monitor_mode, u32 macid);
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void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
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void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len);
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void phydm_fw_trace_handler_8051(void *dm_void, u8 *cmd_buf, u8 cmd_len);
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#endif /* __ODM_DBG_H__ */
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