// SPDX-License-Identifier: GPL-2.0
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2016 Realtek Corporation.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#include "mp_precomp.h"
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#include "phydm_precomp.h"
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/*Set NHM period, threshold, disable ignore cca or not,
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*disable ignore txon or not
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*/
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void phydm_nhm_setting(void *dm_void, u8 nhm_setting)
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{
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struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
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struct ccx_info *ccx_info = &dm->dm_ccx_info;
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if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
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if (nhm_setting == SET_NHM_SETTING) {
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/*Set inexclude_cca, inexclude_txon*/
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9),
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ccx_info->nhm_inexclude_cca);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10),
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ccx_info->nhm_inexclude_txon);
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/*Set NHM period*/
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odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD,
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ccx_info->NHM_period);
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/*Set NHM threshold*/
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odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
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MASKBYTE0, ccx_info->NHM_th[0]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
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MASKBYTE1, ccx_info->NHM_th[1]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
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MASKBYTE2, ccx_info->NHM_th[2]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
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MASKBYTE3, ccx_info->NHM_th[3]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
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MASKBYTE0, ccx_info->NHM_th[4]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
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MASKBYTE1, ccx_info->NHM_th[5]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
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MASKBYTE2, ccx_info->NHM_th[6]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
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MASKBYTE3, ccx_info->NHM_th[7]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0,
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ccx_info->NHM_th[8]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2,
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ccx_info->NHM_th[9]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3,
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ccx_info->NHM_th[10]);
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/*CCX EN*/
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8),
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CCX_EN);
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} else if (nhm_setting == STORE_NHM_SETTING) {
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/*Store prev. disable_ignore_cca, disable_ignore_txon*/
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ccx_info->NHM_inexclude_cca_restore =
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(enum nhm_inexclude_cca)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9));
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ccx_info->NHM_inexclude_txon_restore =
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(enum nhm_inexclude_txon)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10));
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/*Store pervious NHM period*/
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ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(
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dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD);
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/*Store NHM threshold*/
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ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0);
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ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1);
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ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2);
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ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3);
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ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0);
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ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1);
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ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2);
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ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3);
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ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0);
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ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2);
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ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3);
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} else if (nhm_setting == RESTORE_NHM_SETTING) {
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/*Set disable_ignore_cca, disable_ignore_txon*/
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9),
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ccx_info->NHM_inexclude_cca_restore);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10),
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ccx_info->NHM_inexclude_txon_restore);
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/*Set NHM period*/
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odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD,
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ccx_info->NHM_period);
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/*Set NHM threshold*/
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odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
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MASKBYTE0, ccx_info->NHM_th_restore[0]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
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MASKBYTE1, ccx_info->NHM_th_restore[1]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
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MASKBYTE2, ccx_info->NHM_th_restore[2]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
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MASKBYTE3, ccx_info->NHM_th_restore[3]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
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MASKBYTE0, ccx_info->NHM_th_restore[4]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
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MASKBYTE1, ccx_info->NHM_th_restore[5]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
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MASKBYTE2, ccx_info->NHM_th_restore[6]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
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MASKBYTE3, ccx_info->NHM_th_restore[7]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0,
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ccx_info->NHM_th_restore[8]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2,
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ccx_info->NHM_th_restore[9]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3,
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ccx_info->NHM_th_restore[10]);
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} else {
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return;
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}
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}
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else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
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if (nhm_setting == SET_NHM_SETTING) {
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/*Set disable_ignore_cca, disable_ignore_txon*/
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9),
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ccx_info->nhm_inexclude_cca);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10),
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ccx_info->nhm_inexclude_txon);
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/*Set NHM period*/
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odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD,
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ccx_info->NHM_period);
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/*Set NHM threshold*/
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odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
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MASKBYTE0, ccx_info->NHM_th[0]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
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MASKBYTE1, ccx_info->NHM_th[1]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
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MASKBYTE2, ccx_info->NHM_th[2]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
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MASKBYTE3, ccx_info->NHM_th[3]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
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MASKBYTE0, ccx_info->NHM_th[4]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
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MASKBYTE1, ccx_info->NHM_th[5]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
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MASKBYTE2, ccx_info->NHM_th[6]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
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MASKBYTE3, ccx_info->NHM_th[7]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11N, MASKBYTE0,
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ccx_info->NHM_th[8]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2,
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ccx_info->NHM_th[9]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3,
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ccx_info->NHM_th[10]);
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/*CCX EN*/
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(8),
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CCX_EN);
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} else if (nhm_setting == STORE_NHM_SETTING) {
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/*Store prev. disable_ignore_cca, disable_ignore_txon*/
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ccx_info->NHM_inexclude_cca_restore =
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(enum nhm_inexclude_cca)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9));
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ccx_info->NHM_inexclude_txon_restore =
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(enum nhm_inexclude_txon)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10));
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/*Store pervious NHM period*/
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ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(
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dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD);
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/*Store NHM threshold*/
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ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0);
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ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1);
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ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2);
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ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3);
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ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0);
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ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1);
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ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2);
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ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3);
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ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH8_11N, MASKBYTE0);
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ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2);
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ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(
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dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3);
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} else if (nhm_setting == RESTORE_NHM_SETTING) {
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/*Set disable_ignore_cca, disable_ignore_txon*/
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9),
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ccx_info->NHM_inexclude_cca_restore);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10),
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ccx_info->NHM_inexclude_txon_restore);
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/*Set NHM period*/
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odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD,
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ccx_info->NHM_period_restore);
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/*Set NHM threshold*/
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odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
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MASKBYTE0, ccx_info->NHM_th_restore[0]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
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MASKBYTE1, ccx_info->NHM_th_restore[1]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
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MASKBYTE2, ccx_info->NHM_th_restore[2]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
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MASKBYTE3, ccx_info->NHM_th_restore[3]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
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MASKBYTE0, ccx_info->NHM_th_restore[4]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
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MASKBYTE1, ccx_info->NHM_th_restore[5]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
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MASKBYTE2, ccx_info->NHM_th_restore[6]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
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MASKBYTE3, ccx_info->NHM_th_restore[7]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11N, MASKBYTE0,
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ccx_info->NHM_th_restore[8]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2,
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ccx_info->NHM_th_restore[9]);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3,
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ccx_info->NHM_th_restore[10]);
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} else {
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return;
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}
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}
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}
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void phydm_nhm_trigger(void *dm_void)
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{
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struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
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if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
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/*Trigger NHM*/
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1);
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} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
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/*Trigger NHM*/
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0);
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odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1);
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}
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}
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void phydm_get_nhm_result(void *dm_void)
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{
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struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
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u32 value32;
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struct ccx_info *ccx_info = &dm->dm_ccx_info;
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if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
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value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11AC);
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ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0);
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ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8);
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ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16);
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ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24);
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value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11AC);
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ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0);
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ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8);
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ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16);
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ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24);
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value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT11_TO_CNT8_11AC);
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ccx_info->NHM_result[8] = (u8)(value32 & MASKBYTE0);
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ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE1) >> 8);
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ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
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ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
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/*Get NHM duration*/
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value32 = odm_read_4byte(dm, ODM_REG_NHM_DUR_READY_11AC);
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ccx_info->NHM_duration = (u16)(value32 & MASKLWORD);
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}
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else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
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value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11N);
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ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0);
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ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8);
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ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16);
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ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24);
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value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11N);
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ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0);
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ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8);
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ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16);
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ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24);
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value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT9_TO_CNT8_11N);
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ccx_info->NHM_result[8] = (u8)((value32 & MASKBYTE2) >> 16);
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ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE3) >> 24);
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value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT10_TO_CNT11_11N);
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ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
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ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
|
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/*Get NHM duration*/
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value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT10_TO_CNT11_11N);
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ccx_info->NHM_duration = (u16)(value32 & MASKLWORD);
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}
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}
|
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bool phydm_check_nhm_ready(void *dm_void)
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{
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struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
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u32 value32 = 0;
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u8 i;
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bool ret = false;
|
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if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
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value32 =
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odm_get_bb_reg(dm, ODM_REG_CLM_RESULT_11AC, MASKDWORD);
|
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for (i = 0; i < 200; i++) {
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ODM_delay_ms(1);
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if (odm_get_bb_reg(dm, ODM_REG_NHM_DUR_READY_11AC,
|
BIT(17))) {
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ret = 1;
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break;
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}
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}
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}
|
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else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
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value32 = odm_get_bb_reg(dm, ODM_REG_CLM_READY_11N, MASKDWORD);
|
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for (i = 0; i < 200; i++) {
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ODM_delay_ms(1);
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if (odm_get_bb_reg(dm, ODM_REG_NHM_DUR_READY_11AC,
|
BIT(17))) {
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ret = 1;
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break;
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}
|
}
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}
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return ret;
|
}
|
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void phydm_clm_setting(void *dm_void)
|
{
|
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
|
struct ccx_info *ccx_info = &dm->dm_ccx_info;
|
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if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
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odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKLWORD,
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ccx_info->CLM_period); /*4us sample 1 time*/
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odm_set_bb_reg(dm, ODM_REG_CLM_11AC, BIT(8),
|
0x1); /*Enable CCX for CLM*/
|
|
} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
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odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKLWORD,
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ccx_info->CLM_period); /*4us sample 1 time*/
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odm_set_bb_reg(dm, ODM_REG_CLM_11N, BIT(8),
|
0x1); /*Enable CCX for CLM*/
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}
|
|
ODM_RT_TRACE(dm, ODM_COMP_CCX, "[%s] : CLM period = %dus\n", __func__,
|
ccx_info->CLM_period * 4);
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}
|
|
void phydm_clm_trigger(void *dm_void)
|
{
|
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
|
|
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
|
odm_set_bb_reg(dm, ODM_REG_CLM_11AC, BIT(0),
|
0x0); /*Trigger CLM*/
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odm_set_bb_reg(dm, ODM_REG_CLM_11AC, BIT(0), 0x1);
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} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
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odm_set_bb_reg(dm, ODM_REG_CLM_11N, BIT(0),
|
0x0); /*Trigger CLM*/
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odm_set_bb_reg(dm, ODM_REG_CLM_11N, BIT(0), 0x1);
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}
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}
|
|
bool phydm_check_cl_mready(void *dm_void)
|
{
|
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
|
u32 value32 = 0;
|
bool ret = false;
|
|
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
|
value32 = odm_get_bb_reg(
|
dm, ODM_REG_CLM_RESULT_11AC,
|
MASKDWORD); /*make sure CLM calc is ready*/
|
else if (dm->support_ic_type & ODM_IC_11N_SERIES)
|
value32 = odm_get_bb_reg(
|
dm, ODM_REG_CLM_READY_11N,
|
MASKDWORD); /*make sure CLM calc is ready*/
|
|
if ((dm->support_ic_type & ODM_IC_11AC_SERIES) && (value32 & BIT(16)))
|
ret = true;
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else if ((dm->support_ic_type & ODM_IC_11N_SERIES) &&
|
(value32 & BIT(16)))
|
ret = true;
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else
|
ret = false;
|
|
ODM_RT_TRACE(dm, ODM_COMP_CCX, "[%s] : CLM ready = %d\n", __func__,
|
ret);
|
|
return ret;
|
}
|
|
void phydm_get_cl_mresult(void *dm_void)
|
{
|
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
|
struct ccx_info *ccx_info = &dm->dm_ccx_info;
|
|
u32 value32 = 0;
|
|
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
|
value32 = odm_get_bb_reg(dm, ODM_REG_CLM_RESULT_11AC,
|
MASKDWORD); /*read CLM calc result*/
|
else if (dm->support_ic_type & ODM_IC_11N_SERIES)
|
value32 = odm_get_bb_reg(dm, ODM_REG_CLM_RESULT_11N,
|
MASKDWORD); /*read CLM calc result*/
|
|
ccx_info->CLM_result = (u16)(value32 & MASKLWORD);
|
|
ODM_RT_TRACE(dm, ODM_COMP_CCX, "[%s] : CLM result = %dus\n", __func__,
|
ccx_info->CLM_result * 4);
|
}
|
