/******************************************************************************
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* rtl8712_xmit.c
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*
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* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
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* Linux device driver for RTL8192SU
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* Modifications for inclusion into the Linux staging tree are
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* Copyright(c) 2010 Larry Finger. All rights reserved.
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*
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* Contact information:
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* WLAN FAE <wlanfae@realtek.com>
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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******************************************************************************/
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#define _RTL8712_XMIT_C_
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#include "osdep_service.h"
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#include "drv_types.h"
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#include "wifi.h"
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#include "osdep_intf.h"
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#include "usb_ops.h"
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static void dump_xframe(struct _adapter *padapter,
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struct xmit_frame *pxmitframe);
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static void update_txdesc(struct xmit_frame *pxmitframe, uint *pmem, int sz);
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sint _r8712_init_hw_txqueue(struct hw_txqueue *phw_txqueue, u8 ac_tag)
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{
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phw_txqueue->ac_tag = ac_tag;
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switch (ac_tag) {
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case BE_QUEUE_INX:
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phw_txqueue->ff_hwaddr = RTL8712_DMA_BEQ;
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break;
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case BK_QUEUE_INX:
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phw_txqueue->ff_hwaddr = RTL8712_DMA_BKQ;
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break;
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case VI_QUEUE_INX:
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phw_txqueue->ff_hwaddr = RTL8712_DMA_VIQ;
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break;
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case VO_QUEUE_INX:
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phw_txqueue->ff_hwaddr = RTL8712_DMA_VOQ;
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break;
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case BMC_QUEUE_INX:
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phw_txqueue->ff_hwaddr = RTL8712_DMA_BEQ;
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break;
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}
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return _SUCCESS;
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}
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int r8712_txframes_sta_ac_pending(struct _adapter *padapter,
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struct pkt_attrib *pattrib)
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{
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struct sta_info *psta;
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struct tx_servq *ptxservq;
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int priority = pattrib->priority;
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psta = pattrib->psta;
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switch (priority) {
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case 1:
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case 2:
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ptxservq = &(psta->sta_xmitpriv.bk_q);
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break;
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case 4:
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case 5:
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ptxservq = &(psta->sta_xmitpriv.vi_q);
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break;
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case 6:
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case 7:
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ptxservq = &(psta->sta_xmitpriv.vo_q);
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break;
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case 0:
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case 3:
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default:
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ptxservq = &(psta->sta_xmitpriv.be_q);
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break;
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}
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return ptxservq->qcnt;
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}
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static u32 get_ff_hwaddr(struct xmit_frame *pxmitframe)
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{
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u32 addr = 0;
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struct pkt_attrib *pattrib = &pxmitframe->attrib;
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struct _adapter *padapter = pxmitframe->padapter;
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struct dvobj_priv *pdvobj = &padapter->dvobjpriv;
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if (pxmitframe->frame_tag == TXAGG_FRAMETAG) {
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addr = RTL8712_DMA_H2CCMD;
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} else if (pxmitframe->frame_tag == MGNT_FRAMETAG) {
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addr = RTL8712_DMA_MGTQ;
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} else if (pdvobj->nr_endpoint == 6) {
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switch (pattrib->priority) {
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case 0:
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case 3:
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addr = RTL8712_DMA_BEQ;
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break;
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case 1:
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case 2:
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addr = RTL8712_DMA_BKQ;
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break;
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case 4:
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case 5:
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addr = RTL8712_DMA_VIQ;
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break;
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case 6:
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case 7:
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addr = RTL8712_DMA_VOQ;
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break;
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case 0x10:
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case 0x11:
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case 0x12:
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case 0x13:
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addr = RTL8712_DMA_H2CCMD;
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break;
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default:
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addr = RTL8712_DMA_BEQ;
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break;
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}
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} else if (pdvobj->nr_endpoint == 4) {
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switch (pattrib->qsel) {
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case 0:
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case 3:
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case 1:
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case 2:
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addr = RTL8712_DMA_BEQ;/*RTL8712_EP_LO;*/
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break;
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case 4:
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case 5:
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case 6:
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case 7:
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addr = RTL8712_DMA_VOQ;/*RTL8712_EP_HI;*/
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break;
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case 0x10:
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case 0x11:
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case 0x12:
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case 0x13:
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addr = RTL8712_DMA_H2CCMD;
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break;
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default:
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addr = RTL8712_DMA_BEQ;/*RTL8712_EP_LO;*/
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break;
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}
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}
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return addr;
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}
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static struct xmit_frame *dequeue_one_xmitframe(struct xmit_priv *pxmitpriv,
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struct hw_xmit *phwxmit,
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struct tx_servq *ptxservq,
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struct __queue *pframe_queue)
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{
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struct list_head *xmitframe_plist, *xmitframe_phead;
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struct xmit_frame *pxmitframe = NULL;
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xmitframe_phead = &pframe_queue->queue;
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xmitframe_plist = xmitframe_phead->next;
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if (!end_of_queue_search(xmitframe_phead, xmitframe_plist)) {
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pxmitframe = container_of(xmitframe_plist,
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struct xmit_frame, list);
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list_del_init(&pxmitframe->list);
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ptxservq->qcnt--;
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phwxmit->txcmdcnt++;
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}
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return pxmitframe;
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}
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static struct xmit_frame *dequeue_xframe_ex(struct xmit_priv *pxmitpriv,
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struct hw_xmit *phwxmit_i, sint entry)
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{
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unsigned long irqL0;
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struct list_head *sta_plist, *sta_phead;
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struct hw_xmit *phwxmit;
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struct tx_servq *ptxservq = NULL;
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struct __queue *pframe_queue = NULL;
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struct xmit_frame *pxmitframe = NULL;
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int i, inx[4];
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int j, acirp_cnt[4];
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/*entry indx: 0->vo, 1->vi, 2->be, 3->bk.*/
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inx[0] = 0; acirp_cnt[0] = pxmitpriv->voq_cnt;
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inx[1] = 1; acirp_cnt[1] = pxmitpriv->viq_cnt;
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inx[2] = 2; acirp_cnt[2] = pxmitpriv->beq_cnt;
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inx[3] = 3; acirp_cnt[3] = pxmitpriv->bkq_cnt;
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for (i = 0; i < 4; i++) {
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for (j = i + 1; j < 4; j++) {
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if (acirp_cnt[j] < acirp_cnt[i]) {
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swap(acirp_cnt[i], acirp_cnt[j]);
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swap(inx[i], inx[j]);
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}
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}
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}
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spin_lock_irqsave(&pxmitpriv->lock, irqL0);
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for (i = 0; i < entry; i++) {
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phwxmit = phwxmit_i + inx[i];
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sta_phead = &phwxmit->sta_queue->queue;
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sta_plist = sta_phead->next;
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while (!end_of_queue_search(sta_phead, sta_plist)) {
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ptxservq = container_of(sta_plist, struct tx_servq,
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tx_pending);
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pframe_queue = &ptxservq->sta_pending;
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pxmitframe = dequeue_one_xmitframe(pxmitpriv, phwxmit,
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ptxservq, pframe_queue);
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if (pxmitframe) {
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phwxmit->accnt--;
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goto exit_dequeue_xframe_ex;
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}
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sta_plist = sta_plist->next;
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/*Remove sta node when there are no pending packets.*/
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if (list_empty(&pframe_queue->queue)) {
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/* must be done after sta_plist->next
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* and before break
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*/
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list_del_init(&ptxservq->tx_pending);
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}
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}
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}
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exit_dequeue_xframe_ex:
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spin_unlock_irqrestore(&pxmitpriv->lock, irqL0);
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return pxmitframe;
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}
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void r8712_do_queue_select(struct _adapter *padapter,
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struct pkt_attrib *pattrib)
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{
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unsigned int qsel = 0;
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struct dvobj_priv *pdvobj = &padapter->dvobjpriv;
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if (pdvobj->nr_endpoint == 6) {
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qsel = (unsigned int) pattrib->priority;
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} else if (pdvobj->nr_endpoint == 4) {
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qsel = (unsigned int) pattrib->priority;
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if (qsel == 0 || qsel == 3)
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qsel = 3;
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else if (qsel == 1 || qsel == 2)
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qsel = 1;
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else if (qsel == 4 || qsel == 5)
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qsel = 5;
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else if (qsel == 6 || qsel == 7)
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qsel = 7;
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else
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qsel = 3;
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}
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pattrib->qsel = qsel;
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}
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#ifdef CONFIG_R8712_TX_AGGR
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u8 r8712_construct_txaggr_cmd_desc(struct xmit_buf *pxmitbuf)
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{
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struct tx_desc *ptx_desc = (struct tx_desc *)pxmitbuf->pbuf;
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/* Fill up TxCmd Descriptor according as USB FW Tx Aaggregation info.*/
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/* dw0 */
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ptx_desc->txdw0 = cpu_to_le32(CMD_HDR_SZ & 0xffff);
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ptx_desc->txdw0 |=
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cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) &
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0x00ff0000);
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ptx_desc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
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/* dw1 */
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ptx_desc->txdw1 |= cpu_to_le32((0x13 << QSEL_SHT) & 0x00001f00);
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return _SUCCESS;
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}
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u8 r8712_construct_txaggr_cmd_hdr(struct xmit_buf *pxmitbuf)
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{
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struct xmit_frame *pxmitframe = (struct xmit_frame *)
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pxmitbuf->priv_data;
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struct _adapter *padapter = pxmitframe->padapter;
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struct cmd_priv *pcmdpriv = &(padapter->cmdpriv);
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struct cmd_hdr *pcmd_hdr = (struct cmd_hdr *)
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(pxmitbuf->pbuf + TXDESC_SIZE);
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/* Fill up Cmd Header for USB FW Tx Aggregation.*/
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/* dw0 */
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pcmd_hdr->cmd_dw0 = cpu_to_le32((GEN_CMD_CODE(_AMSDU_TO_AMPDU) << 16) |
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(pcmdpriv->cmd_seq << 24));
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pcmdpriv->cmd_seq++;
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return _SUCCESS;
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}
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u8 r8712_append_mpdu_unit(struct xmit_buf *pxmitbuf,
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struct xmit_frame *pxmitframe)
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{
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struct _adapter *padapter = pxmitframe->padapter;
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struct tx_desc *ptx_desc = (struct tx_desc *)pxmitbuf->pbuf;
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int last_txcmdsz = 0;
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int padding_sz = 0;
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/* 802.3->802.11 converter */
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r8712_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
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/* free skb struct */
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r8712_xmit_complete(padapter, pxmitframe);
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if (pxmitframe->attrib.ether_type != 0x0806) {
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if ((pxmitframe->attrib.ether_type != 0x888e) &&
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(pxmitframe->attrib.dhcp_pkt != 1)) {
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r8712_issue_addbareq_cmd(padapter,
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pxmitframe->attrib.priority);
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}
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}
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pxmitframe->last[0] = 1;
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update_txdesc(pxmitframe, (uint *)(pxmitframe->buf_addr),
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pxmitframe->attrib.last_txcmdsz);
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/*padding zero */
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last_txcmdsz = pxmitframe->attrib.last_txcmdsz;
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padding_sz = (8 - (last_txcmdsz % 8));
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if ((last_txcmdsz % 8) != 0) {
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int i;
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for (i = 0; i < padding_sz; i++)
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*(pxmitframe->buf_addr + TXDESC_SIZE + last_txcmdsz +
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i) = 0;
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}
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/* Add the new mpdu's length */
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ptx_desc->txdw0 = cpu_to_le32((ptx_desc->txdw0 & 0xffff0000) |
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((ptx_desc->txdw0 & 0x0000ffff) +
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((TXDESC_SIZE + last_txcmdsz + padding_sz) &
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0x0000ffff)));
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return _SUCCESS;
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}
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u8 r8712_xmitframe_aggr_1st(struct xmit_buf *pxmitbuf,
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struct xmit_frame *pxmitframe)
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{
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/* linux complete context doesn't need to protect */
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pxmitframe->pxmitbuf = pxmitbuf;
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pxmitbuf->priv_data = pxmitframe;
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pxmitframe->pxmit_urb[0] = pxmitbuf->pxmit_urb[0];
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/* buffer addr assoc */
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pxmitframe->buf_addr = pxmitbuf->pbuf + TXDESC_SIZE + CMD_HDR_SZ;
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/*RTL8712_DMA_H2CCMD */
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r8712_construct_txaggr_cmd_desc(pxmitbuf);
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r8712_construct_txaggr_cmd_hdr(pxmitbuf);
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if (r8712_append_mpdu_unit(pxmitbuf, pxmitframe) == _SUCCESS)
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pxmitbuf->aggr_nr = 1;
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return _SUCCESS;
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}
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u16 r8712_xmitframe_aggr_next(struct xmit_buf *pxmitbuf,
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struct xmit_frame *pxmitframe)
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{
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pxmitframe->pxmitbuf = pxmitbuf;
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pxmitbuf->priv_data = pxmitframe;
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pxmitframe->pxmit_urb[0] = pxmitbuf->pxmit_urb[0];
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/* buffer addr assoc */
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pxmitframe->buf_addr = pxmitbuf->pbuf + TXDESC_SIZE +
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(((struct tx_desc *)pxmitbuf->pbuf)->txdw0 & 0x0000ffff);
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if (r8712_append_mpdu_unit(pxmitbuf, pxmitframe) == _SUCCESS) {
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r8712_free_xmitframe_ex(&pxmitframe->padapter->xmitpriv,
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pxmitframe);
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pxmitbuf->aggr_nr++;
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}
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return TXDESC_SIZE +
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(((struct tx_desc *)pxmitbuf->pbuf)->txdw0 & 0x0000ffff);
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}
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u8 r8712_dump_aggr_xframe(struct xmit_buf *pxmitbuf,
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struct xmit_frame *pxmitframe)
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{
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struct _adapter *padapter = pxmitframe->padapter;
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struct dvobj_priv *pdvobj = &padapter->dvobjpriv;
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struct tx_desc *ptxdesc = pxmitbuf->pbuf;
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struct cmd_hdr *pcmd_hdr = (struct cmd_hdr *)
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(pxmitbuf->pbuf + TXDESC_SIZE);
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u16 total_length = (u16) (ptxdesc->txdw0 & 0xffff);
|
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/* use 1st xmitframe as media */
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xmitframe_xmitbuf_attach(pxmitframe, pxmitbuf);
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pcmd_hdr->cmd_dw0 = cpu_to_le32(((total_length - CMD_HDR_SZ) &
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0x0000ffff) | (pcmd_hdr->cmd_dw0 &
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0xffff0000));
|
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/* urb length in cmd_dw1 */
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pcmd_hdr->cmd_dw1 = cpu_to_le32((pxmitbuf->aggr_nr & 0xff)|
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((total_length + TXDESC_SIZE) << 16));
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pxmitframe->last[0] = 1;
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pxmitframe->bpending[0] = false;
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pxmitframe->mem_addr = pxmitbuf->pbuf;
|
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if ((pdvobj->ishighspeed && ((total_length + TXDESC_SIZE) % 0x200) ==
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0) || ((!pdvobj->ishighspeed && ((total_length + TXDESC_SIZE) %
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0x40) == 0))) {
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ptxdesc->txdw0 |= cpu_to_le32
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(((TXDESC_SIZE + OFFSET_SZ + 8) << OFFSET_SHT) &
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0x00ff0000);
|
/*32 bytes for TX Desc + 8 bytes pending*/
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} else {
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ptxdesc->txdw0 |= cpu_to_le32
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(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) &
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0x00ff0000);
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/*default = 32 bytes for TX Desc*/
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}
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r8712_write_port(pxmitframe->padapter, RTL8712_DMA_H2CCMD,
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total_length + TXDESC_SIZE, (u8 *)pxmitframe);
|
|
return _SUCCESS;
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}
|
|
#endif
|
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static void update_txdesc(struct xmit_frame *pxmitframe, uint *pmem, int sz)
|
{
|
uint qsel;
|
struct _adapter *padapter = pxmitframe->padapter;
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struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
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struct qos_priv *pqospriv = &pmlmepriv->qospriv;
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struct security_priv *psecuritypriv = &padapter->securitypriv;
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struct pkt_attrib *pattrib = &pxmitframe->attrib;
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struct tx_desc *ptxdesc = (struct tx_desc *)pmem;
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struct dvobj_priv *pdvobj = &padapter->dvobjpriv;
|
#ifdef CONFIG_R8712_TX_AGGR
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struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
|
#endif
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u8 blnSetTxDescOffset;
|
sint bmcst = IS_MCAST(pattrib->ra);
|
struct ht_priv *phtpriv = &pmlmepriv->htpriv;
|
struct tx_desc txdesc_mp;
|
|
memcpy(&txdesc_mp, ptxdesc, sizeof(struct tx_desc));
|
memset(ptxdesc, 0, sizeof(struct tx_desc));
|
/* offset 0 */
|
ptxdesc->txdw0 |= cpu_to_le32(sz & 0x0000ffff);
|
if (pdvobj->ishighspeed) {
|
if (((sz + TXDESC_SIZE) % 512) == 0)
|
blnSetTxDescOffset = 1;
|
else
|
blnSetTxDescOffset = 0;
|
} else {
|
if (((sz + TXDESC_SIZE) % 64) == 0)
|
blnSetTxDescOffset = 1;
|
else
|
blnSetTxDescOffset = 0;
|
}
|
if (blnSetTxDescOffset) {
|
/* 32 bytes for TX Desc + 8 bytes pending */
|
ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ + 8) <<
|
OFFSET_SHT) & 0x00ff0000);
|
} else {
|
/* default = 32 bytes for TX Desc */
|
ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) <<
|
OFFSET_SHT) & 0x00ff0000);
|
}
|
ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
|
if (pxmitframe->frame_tag == DATA_FRAMETAG) {
|
/* offset 4 */
|
ptxdesc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x1f);
|
|
#ifdef CONFIG_R8712_TX_AGGR
|
/* dirty workaround, need to check if it is aggr cmd. */
|
if ((u8 *)pmem != (u8 *)pxmitframe->pxmitbuf->pbuf) {
|
ptxdesc->txdw0 |= cpu_to_le32
|
((0x3 << TYPE_SHT) & TYPE_MSK);
|
qsel = (uint)(pattrib->qsel & 0x0000001f);
|
if (qsel == 2)
|
qsel = 0;
|
ptxdesc->txdw1 |= cpu_to_le32
|
((qsel << QSEL_SHT) & 0x00001f00);
|
ptxdesc->txdw2 = cpu_to_le32
|
((qsel << RTS_RC_SHT) & 0x001f0000);
|
ptxdesc->txdw6 |= cpu_to_le32
|
((0x5 << RSVD6_SHT) & RSVD6_MSK);
|
} else {
|
ptxdesc->txdw0 |= cpu_to_le32
|
((0x3 << TYPE_SHT) & TYPE_MSK);
|
ptxdesc->txdw1 |= cpu_to_le32
|
((0x13 << QSEL_SHT) & 0x00001f00);
|
qsel = (uint)(pattrib->qsel & 0x0000001f);
|
if (qsel == 2)
|
qsel = 0;
|
ptxdesc->txdw2 = cpu_to_le32
|
((qsel << RTS_RC_SHT) & 0x0001f000);
|
ptxdesc->txdw7 |= cpu_to_le32
|
(pcmdpriv->cmd_seq << 24);
|
pcmdpriv->cmd_seq++;
|
}
|
pattrib->qsel = 0x13;
|
#else
|
qsel = (uint)(pattrib->qsel & 0x0000001f);
|
ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00);
|
#endif
|
if (!pqospriv->qos_option)
|
ptxdesc->txdw1 |= cpu_to_le32(BIT(16));/*Non-QoS*/
|
if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
|
switch (pattrib->encrypt) { /*SEC_TYPE*/
|
case _WEP40_:
|
case _WEP104_:
|
ptxdesc->txdw1 |= cpu_to_le32((0x01 << 22) &
|
0x00c00000);
|
/*KEY_ID when WEP is used;*/
|
ptxdesc->txdw1 |= cpu_to_le32((psecuritypriv->
|
PrivacyKeyIndex << 17) &
|
0x00060000);
|
break;
|
case _TKIP_:
|
case _TKIP_WTMIC_:
|
ptxdesc->txdw1 |= cpu_to_le32((0x02 << 22) &
|
0x00c00000);
|
break;
|
case _AES_:
|
ptxdesc->txdw1 |= cpu_to_le32((0x03 << 22) &
|
0x00c00000);
|
break;
|
case _NO_PRIVACY_:
|
default:
|
break;
|
}
|
}
|
/*offset 8*/
|
if (bmcst)
|
ptxdesc->txdw2 |= cpu_to_le32(BMC);
|
|
/*offset 12*/
|
/* f/w will increase the seqnum by itself, driver pass the
|
* correct priority to fw
|
* fw will check the correct priority for increasing the
|
* seqnum per tid. about usb using 4-endpoint, qsel points out
|
* the correct mapping between AC&Endpoint,
|
* the purpose is that correct mapping lets the MAC release
|
* the AC Queue list correctly.
|
*/
|
ptxdesc->txdw3 = cpu_to_le32((pattrib->priority << SEQ_SHT) &
|
0x0fff0000);
|
if ((pattrib->ether_type != 0x888e) &&
|
(pattrib->ether_type != 0x0806) &&
|
(pattrib->dhcp_pkt != 1)) {
|
/*Not EAP & ARP type data packet*/
|
if (phtpriv->ht_option == 1) { /*B/G/N Mode*/
|
if (phtpriv->ampdu_enable != true)
|
ptxdesc->txdw2 |= cpu_to_le32(BK);
|
}
|
} else {
|
/* EAP data packet and ARP packet.
|
* Use the 1M data rate to send the EAP/ARP packet.
|
* This will maybe make the handshake smooth.
|
*/
|
/*driver uses data rate*/
|
ptxdesc->txdw4 = cpu_to_le32(0x80000000);
|
ptxdesc->txdw5 = cpu_to_le32(0x001f8000);/*1M*/
|
}
|
if (pattrib->pctrl == 1) { /* mp tx packets */
|
struct tx_desc *ptxdesc_mp;
|
|
ptxdesc_mp = &txdesc_mp;
|
/* offset 8 */
|
ptxdesc->txdw2 = ptxdesc_mp->txdw2;
|
if (bmcst)
|
ptxdesc->txdw2 |= cpu_to_le32(BMC);
|
ptxdesc->txdw2 |= cpu_to_le32(BK);
|
/* offset 16 */
|
ptxdesc->txdw4 = ptxdesc_mp->txdw4;
|
/* offset 20 */
|
ptxdesc->txdw5 = ptxdesc_mp->txdw5;
|
pattrib->pctrl = 0;/* reset to zero; */
|
}
|
} else if (pxmitframe->frame_tag == MGNT_FRAMETAG) {
|
/* offset 4 */
|
/* CAM_ID(MAC_ID), default=5; */
|
ptxdesc->txdw1 |= cpu_to_le32((0x05) & 0x1f);
|
qsel = (uint)(pattrib->qsel & 0x0000001f);
|
ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00);
|
ptxdesc->txdw1 |= cpu_to_le32(BIT(16));/* Non-QoS */
|
/* offset 8 */
|
if (bmcst)
|
ptxdesc->txdw2 |= cpu_to_le32(BMC);
|
/* offset 12 */
|
/* f/w will increase the seqnum by itself, driver pass the
|
* correct priority to fw
|
* fw will check the correct priority for increasing the seqnum
|
* per tid. about usb using 4-endpoint, qsel points out the
|
* correct mapping between AC&Endpoint,
|
* the purpose is that correct mapping let the MAC releases
|
* the AC Queue list correctly.
|
*/
|
ptxdesc->txdw3 = cpu_to_le32((pattrib->priority << SEQ_SHT) &
|
0x0fff0000);
|
/* offset 16 */
|
ptxdesc->txdw4 = cpu_to_le32(0x80002040);/*gtest*/
|
/* offset 20 */
|
ptxdesc->txdw5 = cpu_to_le32(0x001f8000);/* gtest 1M */
|
} else if (pxmitframe->frame_tag == TXAGG_FRAMETAG) {
|
/* offset 4 */
|
qsel = 0x13;
|
ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00);
|
} else {
|
/* offset 4 */
|
qsel = (uint)(pattrib->priority & 0x0000001f);
|
ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00);
|
/*offset 8*/
|
/*offset 12*/
|
ptxdesc->txdw3 = cpu_to_le32((pattrib->seqnum << SEQ_SHT) &
|
0x0fff0000);
|
/*offset 16*/
|
ptxdesc->txdw4 = cpu_to_le32(0x80002040);/*gtest*/
|
/*offset 20*/
|
ptxdesc->txdw5 = cpu_to_le32(0x001f9600);/*gtest*/
|
}
|
}
|
|
int r8712_xmitframe_complete(struct _adapter *padapter,
|
struct xmit_priv *pxmitpriv,
|
struct xmit_buf *pxmitbuf)
|
{
|
struct hw_xmit *phwxmits;
|
sint hwentry;
|
struct xmit_frame *pxmitframe = NULL;
|
#ifdef CONFIG_R8712_TX_AGGR
|
struct xmit_frame *p2ndxmitframe = NULL;
|
#else
|
int res = _SUCCESS, xcnt = 0;
|
#endif
|
|
phwxmits = pxmitpriv->hwxmits;
|
hwentry = pxmitpriv->hwxmit_entry;
|
if (!pxmitbuf) {
|
pxmitbuf = r8712_alloc_xmitbuf(pxmitpriv);
|
if (!pxmitbuf)
|
return false;
|
#ifdef CONFIG_R8712_TX_AGGR
|
pxmitbuf->aggr_nr = 0;
|
#endif
|
}
|
/* 1st frame dequeued */
|
pxmitframe = dequeue_xframe_ex(pxmitpriv, phwxmits, hwentry);
|
/* need to remember the 1st frame */
|
if (pxmitframe) {
|
|
#ifdef CONFIG_R8712_TX_AGGR
|
/* 1. dequeue 2nd frame
|
* 2. aggr if 2nd xframe is dequeued, else dump directly
|
*/
|
if (AGGR_NR_HIGH_BOUND > 1)
|
p2ndxmitframe = dequeue_xframe_ex(pxmitpriv, phwxmits,
|
hwentry);
|
if (pxmitframe->frame_tag != DATA_FRAMETAG) {
|
r8712_free_xmitbuf(pxmitpriv, pxmitbuf);
|
return false;
|
}
|
if (p2ndxmitframe)
|
if (p2ndxmitframe->frame_tag != DATA_FRAMETAG) {
|
r8712_free_xmitbuf(pxmitpriv, pxmitbuf);
|
return false;
|
}
|
r8712_xmitframe_aggr_1st(pxmitbuf, pxmitframe);
|
if (p2ndxmitframe) {
|
u16 total_length;
|
|
total_length = r8712_xmitframe_aggr_next(
|
pxmitbuf, p2ndxmitframe);
|
do {
|
p2ndxmitframe = dequeue_xframe_ex(
|
pxmitpriv, phwxmits, hwentry);
|
if (p2ndxmitframe)
|
total_length =
|
r8712_xmitframe_aggr_next(
|
pxmitbuf,
|
p2ndxmitframe);
|
else
|
break;
|
} while (total_length <= 0x1800 &&
|
pxmitbuf->aggr_nr <= AGGR_NR_HIGH_BOUND);
|
}
|
if (pxmitbuf->aggr_nr > 0)
|
r8712_dump_aggr_xframe(pxmitbuf, pxmitframe);
|
|
#else
|
|
xmitframe_xmitbuf_attach(pxmitframe, pxmitbuf);
|
if (pxmitframe->frame_tag == DATA_FRAMETAG) {
|
if (pxmitframe->attrib.priority <= 15)
|
res = r8712_xmitframe_coalesce(padapter,
|
pxmitframe->pkt, pxmitframe);
|
/* always return ndis_packet after
|
* r8712_xmitframe_coalesce
|
*/
|
r8712_xmit_complete(padapter, pxmitframe);
|
}
|
if (res == _SUCCESS)
|
dump_xframe(padapter, pxmitframe);
|
else
|
r8712_free_xmitframe_ex(pxmitpriv, pxmitframe);
|
xcnt++;
|
#endif
|
|
} else { /* pxmitframe == NULL && p2ndxmitframe == NULL */
|
r8712_free_xmitbuf(pxmitpriv, pxmitbuf);
|
return false;
|
}
|
return true;
|
}
|
|
static void dump_xframe(struct _adapter *padapter,
|
struct xmit_frame *pxmitframe)
|
{
|
int t, sz, w_sz;
|
u8 *mem_addr;
|
u32 ff_hwaddr;
|
struct pkt_attrib *pattrib = &pxmitframe->attrib;
|
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
|
struct security_priv *psecuritypriv = &padapter->securitypriv;
|
|
if (pxmitframe->attrib.ether_type != 0x0806) {
|
if (pxmitframe->attrib.ether_type != 0x888e)
|
r8712_issue_addbareq_cmd(padapter, pattrib->priority);
|
}
|
mem_addr = pxmitframe->buf_addr;
|
for (t = 0; t < pattrib->nr_frags; t++) {
|
if (t != (pattrib->nr_frags - 1)) {
|
sz = pxmitpriv->frag_len;
|
sz = sz - 4 - (psecuritypriv->sw_encrypt ? 0 :
|
pattrib->icv_len);
|
pxmitframe->last[t] = 0;
|
} else {
|
sz = pattrib->last_txcmdsz;
|
pxmitframe->last[t] = 1;
|
}
|
update_txdesc(pxmitframe, (uint *)mem_addr, sz);
|
w_sz = sz + TXDESC_SIZE;
|
pxmitframe->mem_addr = mem_addr;
|
pxmitframe->bpending[t] = false;
|
ff_hwaddr = get_ff_hwaddr(pxmitframe);
|
#ifdef CONFIG_R8712_TX_AGGR
|
r8712_write_port(padapter, RTL8712_DMA_H2CCMD, w_sz,
|
(unsigned char *)pxmitframe);
|
#else
|
r8712_write_port(padapter, ff_hwaddr, w_sz,
|
(unsigned char *)pxmitframe);
|
#endif
|
mem_addr += w_sz;
|
mem_addr = (u8 *)RND4(((addr_t)(mem_addr)));
|
}
|
}
|
|
int r8712_xmit_direct(struct _adapter *padapter, struct xmit_frame *pxmitframe)
|
{
|
int res = _SUCCESS;
|
|
res = r8712_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
|
pxmitframe->pkt = NULL;
|
if (res == _SUCCESS)
|
dump_xframe(padapter, pxmitframe);
|
return res;
|
}
|
|
int r8712_xmit_enqueue(struct _adapter *padapter, struct xmit_frame *pxmitframe)
|
{
|
if (r8712_xmit_classifier(padapter, pxmitframe) == _FAIL) {
|
pxmitframe->pkt = NULL;
|
return _FAIL;
|
}
|
return _SUCCESS;
|
}
|
