/*************************************************************************/ /*!
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@Title System Configuration
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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@Description System Configuration functions
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*/ /**************************************************************************/
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#if defined(SUPPORT_ION)
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#include "ion_sys.h"
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#endif /* defined(SUPPORT_ION) */
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#if defined(SUPPORT_PDVFS)
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#include "rgxpdvfs.h"
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#endif
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#include <linux/clkdev.h>
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#include <linux/hardirq.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/delay.h>
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#include <linux/version.h>
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
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#include <linux/rockchip/dvfs.h>
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#endif
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#include "power.h"
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#include "rk_init_v2.h"
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#include "pvrsrv_device.h"
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#include "syscommon.h"
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
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#include <linux/clk-private.h>
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#else
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#include <linux/clk-provider.h>
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#include <linux/pm_runtime.h>
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#include <linux/pm_opp.h>
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#endif
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#include <linux/devfreq_cooling.h>
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#include <linux/thermal.h>
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#include "rgxdevice.h"
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#if !defined(PVR_DVFS) && !defined(SUPPORT_PDVFS)
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typedef struct
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{
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IMG_UINT32 ui32Volt;
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IMG_UINT32 ui32Freq;
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} IMG_OPP;
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#endif
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static const IMG_OPP rkOPPTable[] =
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{
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#if defined(PVR_DVFS) || defined(SUPPORT_PDVFS)
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{ 925, 100000000},
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{ 925, 160000000},
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{ 1025, 266000000},
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{ 1075, 350000000},
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{ 1125, 400000000},
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{ 1200, 500000000},
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#else
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{ 925, 100000000},
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{ 925, 160000000},
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{ 1025, 266000000},
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{ 1075, 350000000},
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{ 1125, 400000000},
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{ 1200, 500000000},
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#endif
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};
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#define RGX_DVFS_STEP (sizeof(rkOPPTable) / sizeof(rkOPPTable[0]))
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#if defined(PVR_DVFS)
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#define DEFAULT_MIN_VF_LEVEL 0
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#else
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#define DEFAULT_MIN_VF_LEVEL 4
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#endif
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//static IMG_UINT32 min_vf_level_val = DEFAULT_MIN_VF_LEVEL;
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//static IMG_UINT32 max_vf_level_val = RGX_DVFS_STEP - 1;
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static struct rk_context *g_platform = NULL;
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
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static int rk33_clk_set_normal_node(struct clk* node, unsigned long rate)
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{
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int ret = 0;
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if (!node) {
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printk("rk33_clk_set_normal_node error \r\n");
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ret = -1;
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}
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ret = clk_set_rate(node, rate);
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if (ret)
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printk("clk_set_rate error \r\n");
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return ret;
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}
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static int rk33_clk_set_dvfs_node(struct dvfs_node *node, unsigned long rate)
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{
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int ret = 0;
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if (!node) {
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printk("rk33_clk_set_dvfs_node error \r\n");
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ret = -1;
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}
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ret = dvfs_clk_set_rate(node, rate);
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if (ret)
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printk("dvfs_clk_set_rate error \r\n");
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return ret;
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}
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void rkSetFrequency(IMG_UINT32 ui32Frequency)
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{
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int ret = 0;
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unsigned long old_freq;
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PVRSRV_ERROR err;
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if (NULL == g_platform)
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panic("oops");
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#if USE_PVR_SPEED_CHANGE
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err = PVRSRVDevicePreClockSpeedChange(g_platform->dev_config->psDevNode, IMG_TRUE, NULL);
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if (err != PVRSRV_OK) {
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return;
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}
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#endif
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if (!g_platform->aclk_gpu_mem || !g_platform->aclk_gpu_cfg) {
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printk("aclk_gpu_mem or aclk_gpu_cfg not init\n");
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return;
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}
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if (!g_platform->gpu_clk_node && !g_platform->clk_gpu) {
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pr_err("%s:clk_gpu & gpu_clk_node is null\n", __func__);
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return;
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}
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if (g_platform->gpu_clk_node)
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old_freq = clk_get_rate(g_platform->gpu_clk_node->clk);
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else if (g_platform->clk_gpu)
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old_freq = clk_get_rate(g_platform->clk_gpu);
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if (old_freq > ui32Frequency) {
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if (g_platform->gpu_clk_node)
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rk33_clk_set_dvfs_node(g_platform->gpu_clk_node, ui32Frequency);
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else if (g_platform->clk_gpu)
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rk33_clk_set_normal_node(g_platform->clk_gpu, ui32Frequency);
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}
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rk33_clk_set_normal_node(g_platform->aclk_gpu_mem, ui32Frequency);
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rk33_clk_set_normal_node(g_platform->aclk_gpu_cfg, ui32Frequency);
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if (old_freq < ui32Frequency) {
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if (g_platform->gpu_clk_node)
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rk33_clk_set_dvfs_node(g_platform->gpu_clk_node, ui32Frequency);
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else if (g_platform->clk_gpu)
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rk33_clk_set_normal_node(g_platform->clk_gpu, ui32Frequency);
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}
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#if USE_PVR_SPEED_CHANGE
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PVRSRVDevicePostClockSpeedChange(g_platform->dev_config->psDevNode, IMG_TRUE, NULL);
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#endif
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}
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//undefine gpu_reg
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void rkSetVoltage(IMG_UINT32 ui32Volt)
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{
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if (NULL == g_platform)
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panic("oops");
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if(regulator_set_voltage(g_platform->gpu_reg, ui32Volt, ui32Volt) != 0)
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{
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PVR_DPF((PVR_DBG_ERROR, "Failed to set gpu power voltage=%d!",ui32Volt));
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}
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}
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#else
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void rkSetFrequency(IMG_UINT32 ui32Frequency)
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{
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int ret = 0;
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unsigned int old_freq, old_volt;
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if (NULL == g_platform)
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panic("oops");
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old_freq = clk_get_rate(g_platform->sclk_gpu_core);
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old_volt = regulator_get_voltage(g_platform->gpu_reg);
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ret = clk_set_rate(g_platform->aclk_gpu_mem, ui32Frequency);
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if (ret) {
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PVR_DPF((PVR_DBG_ERROR, "failed to set aclk_gpu_mem rate: %d\n", ret));
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if (old_volt > 0)
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regulator_set_voltage(g_platform->gpu_reg, old_volt, INT_MAX);
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return;
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}
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ret = clk_set_rate(g_platform->aclk_gpu_cfg, ui32Frequency);
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if (ret) {
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PVR_DPF((PVR_DBG_ERROR, "failed to set aclk_gpu_cfg rate: %d\n", ret));
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clk_set_rate(g_platform->aclk_gpu_mem, old_freq);
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if (old_volt > 0)
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regulator_set_voltage(g_platform->gpu_reg, old_volt, INT_MAX);
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return;
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}
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ret = clk_set_rate(g_platform->sclk_gpu_core, ui32Frequency);
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if (ret) {
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PVR_DPF((PVR_DBG_ERROR, "failed to set sclk_gpu_core rate: %d\n", ret));
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clk_set_rate(g_platform->aclk_gpu_mem, old_freq);
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clk_set_rate(g_platform->aclk_gpu_cfg, old_freq);
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if (old_volt > 0)
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regulator_set_voltage(g_platform->gpu_reg, old_volt, INT_MAX);
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return;
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}
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}
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void rkSetVoltage(IMG_UINT32 ui32Volt)
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{
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if (NULL == g_platform)
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panic("oops");
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if(regulator_set_voltage(g_platform->gpu_reg, ui32Volt, INT_MAX) != 0)
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{
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PVR_DPF((PVR_DBG_ERROR, "Failed to set gpu power voltage=%d!",ui32Volt));
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}
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}
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#endif
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static void RgxEnableClock(struct rk_context *platform)
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{
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
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if (!platform->gpu_clk_node && !platform->clk_gpu)
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{
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printk("gpu_clk_node and clk_gpu are both null\n");
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return;
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}
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#else
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if (!platform->sclk_gpu_core)
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{
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printk("sclk_gpu_core is null\n");
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return;
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}
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#endif
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if (platform->aclk_gpu_mem && platform->aclk_gpu_cfg && !platform->gpu_active) {
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
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if (platform->gpu_clk_node)
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dvfs_clk_prepare_enable(platform->gpu_clk_node);
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else if (platform->clk_gpu)
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clk_prepare_enable(platform->clk_gpu);
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#else
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clk_prepare_enable(platform->sclk_gpu_core);
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#endif
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clk_prepare_enable(platform->aclk_gpu_mem);
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clk_prepare_enable(platform->aclk_gpu_cfg);
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platform->gpu_active = IMG_TRUE;
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} else {
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PVR_DPF((PVR_DBG_WARNING, "Failed to enable clock!"));
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}
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}
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static void RgxDisableClock(struct rk_context *platform)
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{
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
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if (!platform->gpu_clk_node && !platform->clk_gpu) {
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printk("gpu_clk_node and clk_gpu are both null\n");
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return;
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}
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#else
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if (!platform->sclk_gpu_core) {
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printk("sclk_gpu_core is null");
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return;
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}
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#endif
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if (platform->aclk_gpu_mem && platform->aclk_gpu_cfg && platform->gpu_active) {
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clk_disable_unprepare(platform->aclk_gpu_cfg);
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clk_disable_unprepare(platform->aclk_gpu_mem);
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
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if (platform->gpu_clk_node)
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dvfs_clk_disable_unprepare(platform->gpu_clk_node);
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else if (platform->clk_gpu)
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clk_disable_unprepare(platform->clk_gpu);
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#else
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clk_disable_unprepare(platform->sclk_gpu_core);
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#endif
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platform->gpu_active = IMG_FALSE;
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} else {
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PVR_DPF((PVR_DBG_WARNING, "Failed to disable clock!"));
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}
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}
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#if OPEN_GPU_PD
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
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/*
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* The power management
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* software must power down pd_gpu_1 before power down pd_gpu_0,
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* and power up pd_gpu_1 after power up pd_gpu_0.
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*/
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static void RgxEnablePower(struct rk_context *platform)
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{
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if (!platform->bEnablePd && platform->pd_gpu_0 && platform->pd_gpu_1) {
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clk_prepare_enable(platform->pd_gpu_0);
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clk_prepare_enable(platform->pd_gpu_1);
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platform->bEnablePd = IMG_TRUE;
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} else {
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PVR_DPF((PVR_DBG_WARNING, "Failed to enable gpu_pd clock!"));
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}
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}
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static void RgxDisablePower(struct rk_context *platform)
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{
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if (platform->bEnablePd && platform->pd_gpu_0 && platform->pd_gpu_1) {
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clk_disable_unprepare(platform->pd_gpu_1);
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clk_disable_unprepare(platform->pd_gpu_0);
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platform->bEnablePd = IMG_FALSE;
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} else {
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PVR_DPF((PVR_DBG_WARNING, "Failed to enable gpu_pd clock!"));
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}
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}
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#else
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static void RgxEnablePower(struct rk_context *platform)
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{
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struct device *dev = (struct device *)platform->dev_config->pvOSDevice;
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if (!platform->bEnablePd) {
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pm_runtime_get_sync(dev);
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platform->bEnablePd = IMG_TRUE;
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} else {
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PVR_DPF((PVR_DBG_WARNING, "Failed to enable gpu_pd clock!"));
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}
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}
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static void RgxDisablePower(struct rk_context *platform)
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{
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struct device *dev = (struct device *)platform->dev_config->pvOSDevice;
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if (platform->bEnablePd) {
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pm_runtime_put(dev);
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platform->bEnablePd = IMG_FALSE;
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} else {
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PVR_DPF((PVR_DBG_WARNING, "Failed to enable gpu_pd clock!"));
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}
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}
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#endif
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#endif //end of OPEN_GPU_PD
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void RgxResume(struct rk_context *platform)
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{
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#if OPEN_GPU_PD
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RgxEnablePower(platform);
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#endif
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RgxEnableClock(platform);
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}
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void RgxSuspend(struct rk_context *platform)
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{
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RgxDisableClock(platform);
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#if OPEN_GPU_PD
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RgxDisablePower(platform);
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#endif
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}
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PVRSRV_ERROR RkPrePowerState(IMG_HANDLE hSysData,
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PVRSRV_DEV_POWER_STATE eNewPowerState,
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PVRSRV_DEV_POWER_STATE eCurrentPowerState,
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IMG_BOOL bForced)
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{
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struct rk_context *platform = (struct rk_context *)hSysData;
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if (eNewPowerState == PVRSRV_DEV_POWER_STATE_ON)
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RgxResume(platform);
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return PVRSRV_OK;
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}
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PVRSRV_ERROR RkPostPowerState(IMG_HANDLE hSysData,
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PVRSRV_DEV_POWER_STATE eNewPowerState,
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PVRSRV_DEV_POWER_STATE eCurrentPowerState,
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IMG_BOOL bForced)
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{
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struct rk_context *platform = (struct rk_context *)hSysData;
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if (eNewPowerState == PVRSRV_DEV_POWER_STATE_OFF)
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RgxSuspend(platform);
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return PVRSRV_OK;
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}
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#if defined(CONFIG_DEVFREQ_THERMAL) && defined(PVR_DVFS)
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/*
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* This model is primarily designed for the Juno platform. It may not be
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* suitable for other platforms.
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*/
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#define FALLBACK_STATIC_TEMPERATURE 55000
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static u32 dynamic_coefficient;
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static u32 static_coefficient;
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static s32 ts[4];
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static struct thermal_zone_device *gpu_tz;
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static unsigned long model_static_power(struct devfreq *devfreq,
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unsigned long voltage)
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{
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 3, 0)
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unsigned long temperature;
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#else
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int temperature;
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#endif
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unsigned long temp;
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unsigned long temp_squared, temp_cubed, temp_scaling_factor;
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const unsigned long voltage_cubed = (voltage * voltage * voltage) >> 10;
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if (gpu_tz) {
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int ret;
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ret = gpu_tz->ops->get_temp(gpu_tz, &temperature);
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if (ret) {
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pr_warn_ratelimited("Error reading temperature for gpu thermal zone: %d\n",
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ret);
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temperature = FALLBACK_STATIC_TEMPERATURE;
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}
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} else {
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temperature = FALLBACK_STATIC_TEMPERATURE;
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}
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/* Calculate the temperature scaling factor. To be applied to the
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* voltage scaled power.
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*/
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temp = temperature / 1000;
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temp_squared = temp * temp;
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temp_cubed = temp_squared * temp;
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temp_scaling_factor =
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(ts[3] * temp_cubed)
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+ (ts[2] * temp_squared)
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+ (ts[1] * temp)
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+ ts[0];
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return (((static_coefficient * voltage_cubed) >> 20)
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* temp_scaling_factor)
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/ 1000000;
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}
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static unsigned long model_dynamic_power(struct devfreq *devfreq,
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unsigned long freq,
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unsigned long voltage)
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{
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/* The inputs: freq (f) is in Hz, and voltage (v) in mV.
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* The coefficient (c) is in mW/(MHz mV mV).
|
*
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* This function calculates the dynamic power after this formula:
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* Pdyn (mW) = c (mW/(MHz*mV*mV)) * v (mV) * v (mV) * f (MHz)
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*/
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const unsigned long v2 = (voltage * voltage) / 1000; /* m*(V*V) */
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const unsigned long f_mhz = freq / 1000000; /* MHz */
|
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return (dynamic_coefficient * v2 * f_mhz) / 1000000; /* mW */
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}
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|
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
|
struct devfreq_cooling_ops rk_power_model_simple_ops = {
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#else
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struct devfreq_cooling_power rk_power_model_simple_ops = {
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#endif
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.get_static_power = model_static_power,
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.get_dynamic_power = model_dynamic_power,
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};
|
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int rk_power_model_simple_init(struct device *dev)
|
{
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struct device_node *power_model_node;
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const char *tz_name;
|
u32 static_power, dynamic_power;
|
u32 voltage, voltage_squared, voltage_cubed, frequency;
|
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power_model_node = of_get_child_by_name(dev->of_node,
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"power_model");
|
if (!power_model_node) {
|
dev_err(dev, "could not find power_model node\n");
|
return -ENODEV;
|
}
|
if (!of_device_is_compatible(power_model_node,
|
"arm,mali-simple-power-model")) {
|
dev_err(dev, "power_model incompatible with simple power model\n");
|
return -ENODEV;
|
}
|
|
if (of_property_read_string(power_model_node, "thermal-zone",
|
&tz_name)) {
|
dev_err(dev, "ts in power_model not available\n");
|
return -EINVAL;
|
}
|
|
gpu_tz = thermal_zone_get_zone_by_name(tz_name);
|
if (IS_ERR(gpu_tz)) {
|
pr_warn_ratelimited("Error getting gpu thermal zone (%ld), not yet ready?\n",
|
PTR_ERR(gpu_tz));
|
gpu_tz = NULL;
|
|
return -EPROBE_DEFER;
|
}
|
|
if (of_property_read_u32(power_model_node, "static-power",
|
&static_power)) {
|
dev_err(dev, "static-power in power_model not available\n");
|
return -EINVAL;
|
}
|
if (of_property_read_u32(power_model_node, "dynamic-power",
|
&dynamic_power)) {
|
dev_err(dev, "dynamic-power in power_model not available\n");
|
return -EINVAL;
|
}
|
if (of_property_read_u32(power_model_node, "voltage",
|
&voltage)) {
|
dev_err(dev, "voltage in power_model not available\n");
|
return -EINVAL;
|
}
|
if (of_property_read_u32(power_model_node, "frequency",
|
&frequency)) {
|
dev_err(dev, "frequency in power_model not available\n");
|
return -EINVAL;
|
}
|
voltage_squared = (voltage * voltage) / 1000;
|
voltage_cubed = voltage * voltage * voltage;
|
static_coefficient = (static_power << 20) / (voltage_cubed >> 10);
|
dynamic_coefficient = (((dynamic_power * 1000) / voltage_squared)
|
* 1000) / frequency;
|
|
if (of_property_read_u32_array(power_model_node, "ts", (u32 *)ts, 4)) {
|
dev_err(dev, "ts in power_model not available\n");
|
return -EINVAL;
|
}
|
|
return 0;
|
}
|
#endif
|
|
void RgxRkUnInit(struct rk_context *platform)
|
{
|
struct device *dev = (struct device *)platform->dev_config->pvOSDevice;
|
|
RgxSuspend(platform);
|
|
#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
|
if (platform->gpu_clk_node) {
|
clk_put_dvfs_node(platform->gpu_clk_node);
|
platform->gpu_clk_node = NULL;
|
} else if (platform->clk_gpu) {
|
devm_clk_put(dev, platform->clk_gpu);
|
platform->clk_gpu = NULL;
|
}
|
#else
|
if (platform->sclk_gpu_core) {
|
devm_clk_put(dev, platform->sclk_gpu_core);
|
platform->sclk_gpu_core = NULL;
|
}
|
#endif
|
|
if (platform->aclk_gpu_cfg) {
|
devm_clk_put(dev, platform->aclk_gpu_cfg);
|
platform->aclk_gpu_cfg = NULL;
|
}
|
if (platform->aclk_gpu_mem) {
|
devm_clk_put(dev, platform->aclk_gpu_mem);
|
platform->aclk_gpu_mem = NULL;
|
}
|
#if OPEN_GPU_PD
|
#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
|
if (platform->pd_gpu_1) {
|
devm_clk_put(dev, platform->pd_gpu_1);
|
platform->pd_gpu_1 = NULL;
|
}
|
if (platform->pd_gpu_0) {
|
devm_clk_put(dev, platform->pd_gpu_0);
|
platform->pd_gpu_0 = NULL;
|
}
|
#else
|
pm_runtime_disable(dev);
|
#endif
|
#endif
|
devm_kfree(dev, platform);
|
|
}
|
|
struct rk_context *RgxRkInit(PVRSRV_DEVICE_CONFIG* psDevConfig)
|
{
|
struct device *dev = (struct device *)psDevConfig->pvOSDevice;
|
struct rk_context *platform;
|
RGX_DATA* psRGXData = (RGX_DATA*)psDevConfig->hDevData;
|
|
platform = devm_kzalloc(dev, sizeof(struct rk_context), GFP_KERNEL);
|
if (NULL == platform) {
|
PVR_DPF((PVR_DBG_ERROR, "RgxRkInit: Failed to kzalloc rk_context"));
|
return NULL;
|
}
|
|
g_platform = platform;
|
|
if (!dev->dma_mask)
|
dev->dma_mask = &dev->coherent_dma_mask;
|
|
PVR_DPF((PVR_DBG_ERROR, "%s: dma_mask = %llx", __func__, dev->coherent_dma_mask));
|
|
platform->dev_config = psDevConfig;
|
platform->gpu_active = IMG_FALSE;
|
|
#if defined(PVR_DVFS) || defined(SUPPORT_PDVFS)
|
//psDevConfig->sDVFS.sDVFSDeviceCfg.pasOPPTable = rkOPPTable;
|
//psDevConfig->sDVFS.sDVFSDeviceCfg.ui32OPPTableSize = RGX_DVFS_STEP;
|
psDevConfig->sDVFS.sDVFSDeviceCfg.pfnSetFrequency = rkSetFrequency;
|
psDevConfig->sDVFS.sDVFSDeviceCfg.pfnSetVoltage = rkSetVoltage;
|
#if defined(CONFIG_DEVFREQ_THERMAL)
|
psDevConfig->sDVFS.sDVFSDeviceCfg.psPowerOps = &rk_power_model_simple_ops;
|
#endif
|
#endif
|
|
#if OPEN_GPU_PD
|
platform->bEnablePd = IMG_FALSE;
|
#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
|
platform->pd_gpu_0 = devm_clk_get(dev, "pd_gpu_0");
|
if (IS_ERR_OR_NULL(platform->pd_gpu_0)) {
|
PVR_DPF((PVR_DBG_ERROR, "RgxRkInit: Failed to find pd_gpu_0 clock source"));
|
goto fail0;
|
}
|
|
platform->pd_gpu_1 = devm_clk_get(dev, "pd_gpu_1");
|
if (IS_ERR_OR_NULL(platform->pd_gpu_1)) {
|
PVR_DPF((PVR_DBG_ERROR, "RgxRkInit: Failed to find pd_gpu_1 clock source"));
|
goto fail1;
|
}
|
#else
|
pm_runtime_enable(dev);
|
#endif
|
#endif
|
|
platform->aclk_gpu_mem = devm_clk_get(dev, "aclk_gpu_mem");
|
if (IS_ERR_OR_NULL(platform->aclk_gpu_mem)) {
|
PVR_DPF((PVR_DBG_ERROR, "RgxRkInit: Failed to find aclk_gpu_mem clock source"));
|
goto fail2;
|
}
|
|
platform->aclk_gpu_cfg = devm_clk_get(dev, "aclk_gpu_cfg");
|
if (IS_ERR_OR_NULL(platform->aclk_gpu_cfg)) {
|
PVR_DPF((PVR_DBG_ERROR, "RgxRkInit: Failed to find aclk_gpu_cfg clock source"));
|
goto fail3;
|
}
|
#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
|
platform->gpu_clk_node = clk_get_dvfs_node("clk_gpu");
|
if (IS_ERR_OR_NULL(platform->gpu_clk_node))
|
{
|
PVR_DPF((PVR_DBG_ERROR, "RgxRkInit: GPU Dvfs is disabled"));
|
platform->clk_gpu = devm_clk_get(dev, "clk_gpu");
|
if (IS_ERR_OR_NULL(platform->clk_gpu)) {
|
PVR_DPF((PVR_DBG_ERROR, "RgxRkInit: Failed to find clk_gpu clock source"));
|
goto fail4;
|
} else {
|
rk33_clk_set_normal_node(platform->clk_gpu, RK33_DEFAULT_CLOCK);
|
}
|
} else {
|
rk33_clk_set_dvfs_node(platform->gpu_clk_node, RK33_DEFAULT_CLOCK);
|
}
|
#else
|
platform->sclk_gpu_core = devm_clk_get(dev, "sclk_gpu_core");
|
if (IS_ERR_OR_NULL(platform->sclk_gpu_core)) {
|
PVR_DPF((PVR_DBG_ERROR, "RgxRkInit: Failed to find sclk_gpu_core clock source"));
|
goto fail4;
|
}
|
|
platform->gpu_reg = devm_regulator_get_optional(dev, "logic");
|
if (IS_ERR_OR_NULL(platform->gpu_reg)) {
|
/*if (dev_pm_opp_of_add_table(dev)) {
|
|
} else {
|
}*/
|
PVR_DPF((PVR_DBG_ERROR, "RgxRkInit: devm_regulator_get_optional failed."));
|
goto fail5;
|
}
|
|
clk_set_rate(platform->sclk_gpu_core, RK33_DEFAULT_CLOCK * ONE_MHZ);
|
|
if(psRGXData && psRGXData->psRGXTimingInfo)
|
{
|
psRGXData->psRGXTimingInfo->ui32CoreClockSpeed = clk_get_rate(platform->sclk_gpu_core);
|
psRGXData->psRGXTimingInfo->ui32CoreVoltage = regulator_get_voltage(platform->gpu_reg);
|
}
|
#endif
|
clk_set_rate(platform->aclk_gpu_mem, RK33_DEFAULT_CLOCK * ONE_MHZ);
|
clk_set_rate(platform->aclk_gpu_cfg, RK33_DEFAULT_CLOCK * ONE_MHZ);
|
|
|
|
(void) RkPrePowerState(platform,
|
PVRSRV_DEV_POWER_STATE_ON,
|
PVRSRV_DEV_POWER_STATE_DEFAULT,
|
IMG_FALSE);
|
|
RgxResume(platform);
|
|
return platform;
|
|
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
|
fail5:
|
devm_clk_put(dev, platform->sclk_gpu_core);
|
platform->sclk_gpu_core = NULL;
|
#endif
|
fail4:
|
devm_clk_put(dev, platform->aclk_gpu_cfg);
|
platform->aclk_gpu_cfg = NULL;
|
fail3:
|
devm_clk_put(dev, platform->aclk_gpu_mem);
|
platform->aclk_gpu_mem = NULL;
|
fail2:
|
|
#if OPEN_GPU_PD && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
|
devm_clk_put(dev, platform->pd_gpu_1);
|
platform->pd_gpu_1 = NULL;
|
fail1:
|
devm_clk_put(dev, platform->pd_gpu_0);
|
platform->pd_gpu_0 = NULL;
|
fail0:
|
devm_kfree(dev, platform);
|
return NULL;
|
#else
|
devm_kfree(dev, platform);
|
return NULL;
|
#endif //end of OPEN_GPU_PD
|
|
}
|
|
|
#if defined(SUPPORT_ION)
|
struct ion_device *g_psIonDev;
|
|
PVRSRV_ERROR IonInit(void *phPrivateData)
|
{
|
g_psIonDev = NULL;
|
return PVRSRV_OK;
|
}
|
|
struct ion_device *IonDevAcquire(void)
|
{
|
return g_psIonDev;
|
}
|
|
void IonDevRelease(struct ion_device *psIonDev)
|
{
|
/* Nothing to do, sanity check the pointer we're passed back */
|
PVR_ASSERT(psIonDev == g_psIonDev);
|
}
|
|
void IonDeinit(void)
|
{
|
g_psIonDev = NULL;
|
}
|
#endif /* defined(SUPPORT_ION) */
|
