// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2013-2016 Freescale Semiconductor Inc.
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* Copyright 2016-2018 NXP
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*/
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#ifndef _FSL_DPRTC_CMD_H
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#define _FSL_DPRTC_CMD_H
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/* DPRTC Version */
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#define DPRTC_VER_MAJOR 2
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#define DPRTC_VER_MINOR 0
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/* Command versioning */
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#define DPRTC_CMD_BASE_VERSION 1
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#define DPRTC_CMD_ID_OFFSET 4
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#define DPRTC_CMD(id) (((id) << DPRTC_CMD_ID_OFFSET) | DPRTC_CMD_BASE_VERSION)
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/* Command IDs */
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#define DPRTC_CMDID_CLOSE DPRTC_CMD(0x800)
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#define DPRTC_CMDID_OPEN DPRTC_CMD(0x810)
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#define DPRTC_CMDID_CREATE DPRTC_CMD(0x910)
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#define DPRTC_CMDID_DESTROY DPRTC_CMD(0x990)
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#define DPRTC_CMDID_GET_API_VERSION DPRTC_CMD(0xa10)
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#define DPRTC_CMDID_ENABLE DPRTC_CMD(0x002)
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#define DPRTC_CMDID_DISABLE DPRTC_CMD(0x003)
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#define DPRTC_CMDID_GET_ATTR DPRTC_CMD(0x004)
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#define DPRTC_CMDID_RESET DPRTC_CMD(0x005)
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#define DPRTC_CMDID_IS_ENABLED DPRTC_CMD(0x006)
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#define DPRTC_CMDID_SET_IRQ_ENABLE DPRTC_CMD(0x012)
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#define DPRTC_CMDID_GET_IRQ_ENABLE DPRTC_CMD(0x013)
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#define DPRTC_CMDID_SET_IRQ_MASK DPRTC_CMD(0x014)
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#define DPRTC_CMDID_GET_IRQ_MASK DPRTC_CMD(0x015)
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#define DPRTC_CMDID_GET_IRQ_STATUS DPRTC_CMD(0x016)
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#define DPRTC_CMDID_CLEAR_IRQ_STATUS DPRTC_CMD(0x017)
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#define DPRTC_CMDID_SET_CLOCK_OFFSET DPRTC_CMD(0x1d0)
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#define DPRTC_CMDID_SET_FREQ_COMPENSATION DPRTC_CMD(0x1d1)
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#define DPRTC_CMDID_GET_FREQ_COMPENSATION DPRTC_CMD(0x1d2)
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#define DPRTC_CMDID_GET_TIME DPRTC_CMD(0x1d3)
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#define DPRTC_CMDID_SET_TIME DPRTC_CMD(0x1d4)
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#define DPRTC_CMDID_SET_ALARM DPRTC_CMD(0x1d5)
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#define DPRTC_CMDID_SET_PERIODIC_PULSE DPRTC_CMD(0x1d6)
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#define DPRTC_CMDID_CLEAR_PERIODIC_PULSE DPRTC_CMD(0x1d7)
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#define DPRTC_CMDID_SET_EXT_TRIGGER DPRTC_CMD(0x1d8)
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#define DPRTC_CMDID_CLEAR_EXT_TRIGGER DPRTC_CMD(0x1d9)
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#define DPRTC_CMDID_GET_EXT_TRIGGER_TIMESTAMP DPRTC_CMD(0x1dA)
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/* Macros for accessing command fields smaller than 1byte */
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#define DPRTC_MASK(field) \
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GENMASK(DPRTC_##field##_SHIFT + DPRTC_##field##_SIZE - 1, \
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DPRTC_##field##_SHIFT)
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#define dprtc_get_field(var, field) \
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(((var) & DPRTC_MASK(field)) >> DPRTC_##field##_SHIFT)
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#pragma pack(push, 1)
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struct dprtc_cmd_open {
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__le32 dprtc_id;
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};
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struct dprtc_cmd_destroy {
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__le32 object_id;
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};
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#define DPRTC_ENABLE_SHIFT 0
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#define DPRTC_ENABLE_SIZE 1
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struct dprtc_rsp_is_enabled {
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u8 en;
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};
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struct dprtc_cmd_get_irq {
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__le32 pad;
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u8 irq_index;
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};
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struct dprtc_cmd_set_irq_enable {
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u8 en;
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u8 pad[3];
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u8 irq_index;
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};
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struct dprtc_rsp_get_irq_enable {
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u8 en;
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};
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struct dprtc_cmd_set_irq_mask {
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__le32 mask;
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u8 irq_index;
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};
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struct dprtc_rsp_get_irq_mask {
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__le32 mask;
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};
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struct dprtc_cmd_get_irq_status {
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__le32 status;
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u8 irq_index;
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};
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struct dprtc_rsp_get_irq_status {
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__le32 status;
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};
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struct dprtc_cmd_clear_irq_status {
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__le32 status;
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u8 irq_index;
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};
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struct dprtc_rsp_get_attributes {
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__le32 pad;
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__le32 id;
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};
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struct dprtc_cmd_set_clock_offset {
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__le64 offset;
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};
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struct dprtc_get_freq_compensation {
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__le32 freq_compensation;
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};
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struct dprtc_time {
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__le64 time;
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};
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struct dprtc_rsp_get_api_version {
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__le16 major;
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__le16 minor;
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};
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#pragma pack(pop)
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#endif /* _FSL_DPRTC_CMD_H */
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