/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2003 Digi International (www.digi.com)
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* Scott H Kilau <Scott_Kilau at digi dot com>
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*/
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#ifndef _DGNC_CLS_H
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#define _DGNC_CLS_H
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/**
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* struct cls_uart_struct - Per channel/port Classic UART.
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*
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* key - W = read write
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* - R = read only
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* - U = unused
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*
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* @txrx: (WR) Holding Register.
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* @ier: (WR) Interrupt Enable Register.
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* @isr_fcr: (WR) Interrupt Status Register/Fifo Control Register.
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* @lcr: (WR) Line Control Register.
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* @mcr: (WR) Modem Control Register.
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* @lsr: (WR) Line Status Register.
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* @msr: (WR) Modem Status Register.
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* @spr: (WR) Scratch Pad Register.
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*/
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struct cls_uart_struct {
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u8 txrx;
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u8 ier;
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u8 isr_fcr;
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u8 lcr;
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u8 mcr;
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u8 lsr;
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u8 msr;
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u8 spr;
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};
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/* Where to read the interrupt register (8bits) */
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#define UART_CLASSIC_POLL_ADDR_OFFSET 0x40
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#define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF
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#define UART_16654_FCR_TXTRIGGER_16 0x10
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#define UART_16654_FCR_RXTRIGGER_16 0x40
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#define UART_16654_FCR_RXTRIGGER_56 0x80
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/* Received CTS/RTS change of state */
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#define UART_IIR_CTSRTS 0x20
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/* Receiver data TIMEOUT */
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#define UART_IIR_RDI_TIMEOUT 0x0C
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/*
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* These are the EXTENDED definitions for the Exar 654's Interrupt
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* Enable Register.
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*/
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#define UART_EXAR654_EFR_ECB 0x10 /* Enhanced control bit */
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#define UART_EXAR654_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
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#define UART_EXAR654_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
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#define UART_EXAR654_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
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#define UART_EXAR654_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow Control Enable */
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#define UART_EXAR654_IER_XOFF 0x20 /* Xoff Interrupt Enable */
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#define UART_EXAR654_IER_RTSDTR 0x40 /* Output Interrupt Enable */
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#define UART_EXAR654_IER_CTSDSR 0x80 /* Input Interrupt Enable */
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extern struct board_ops dgnc_cls_ops;
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#endif /* _DGNC_CLS_H */
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