// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2003 Digi International (www.digi.com)
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* Scott H Kilau <Scott_Kilau at digi dot com>
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/serial.h>
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#include <linux/serial_reg.h>
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#include <linux/pci.h>
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#include "dgnc_driver.h"
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#include "dgnc_cls.h"
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#include "dgnc_tty.h"
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static inline void cls_set_cts_flow_control(struct channel_t *ch)
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{
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unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
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unsigned char ier = readb(&ch->ch_cls_uart->ier);
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unsigned char isr_fcr = 0;
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/*
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* The Enhanced Register Set may only be accessed when
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* the Line Control Register is set to 0xBFh.
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*/
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
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/* Turn on CTS flow control, turn off IXON flow control */
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isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR);
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isr_fcr &= ~(UART_EXAR654_EFR_IXON);
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writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
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/* Write old LCR value back out, which turns enhanced access off */
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writeb(lcrb, &ch->ch_cls_uart->lcr);
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/*
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* Enable interrupts for CTS flow, turn off interrupts for
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* received XOFF chars
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*/
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ier |= (UART_EXAR654_IER_CTSDSR);
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ier &= ~(UART_EXAR654_IER_XOFF);
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writeb(ier, &ch->ch_cls_uart->ier);
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/* Set the usual FIFO values */
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writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
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writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
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UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
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&ch->ch_cls_uart->isr_fcr);
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ch->ch_t_tlevel = 16;
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}
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static inline void cls_set_ixon_flow_control(struct channel_t *ch)
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{
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unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
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unsigned char ier = readb(&ch->ch_cls_uart->ier);
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unsigned char isr_fcr = 0;
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/*
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* The Enhanced Register Set may only be accessed when
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* the Line Control Register is set to 0xBFh.
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*/
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
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/* Turn on IXON flow control, turn off CTS flow control */
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isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON);
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isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR);
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writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
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/* Now set our current start/stop chars while in enhanced mode */
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writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
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writeb(0, &ch->ch_cls_uart->lsr);
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writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
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writeb(0, &ch->ch_cls_uart->spr);
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/* Write old LCR value back out, which turns enhanced access off */
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writeb(lcrb, &ch->ch_cls_uart->lcr);
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/*
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* Disable interrupts for CTS flow, turn on interrupts for
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* received XOFF chars
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*/
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ier &= ~(UART_EXAR654_IER_CTSDSR);
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ier |= (UART_EXAR654_IER_XOFF);
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writeb(ier, &ch->ch_cls_uart->ier);
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/* Set the usual FIFO values */
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writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
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writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
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UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
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&ch->ch_cls_uart->isr_fcr);
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}
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static inline void cls_set_no_output_flow_control(struct channel_t *ch)
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{
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unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
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unsigned char ier = readb(&ch->ch_cls_uart->ier);
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unsigned char isr_fcr = 0;
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/*
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* The Enhanced Register Set may only be accessed when
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* the Line Control Register is set to 0xBFh.
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*/
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
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/* Turn off IXON flow control, turn off CTS flow control */
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isr_fcr |= (UART_EXAR654_EFR_ECB);
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isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON);
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writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
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/* Write old LCR value back out, which turns enhanced access off */
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writeb(lcrb, &ch->ch_cls_uart->lcr);
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/*
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* Disable interrupts for CTS flow, turn off interrupts for
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* received XOFF chars
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*/
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ier &= ~(UART_EXAR654_IER_CTSDSR);
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ier &= ~(UART_EXAR654_IER_XOFF);
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writeb(ier, &ch->ch_cls_uart->ier);
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/* Set the usual FIFO values */
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writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
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writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
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UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
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&ch->ch_cls_uart->isr_fcr);
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ch->ch_r_watermark = 0;
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ch->ch_t_tlevel = 16;
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ch->ch_r_tlevel = 16;
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}
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static inline void cls_set_rts_flow_control(struct channel_t *ch)
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{
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unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
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unsigned char ier = readb(&ch->ch_cls_uart->ier);
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unsigned char isr_fcr = 0;
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/*
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* The Enhanced Register Set may only be accessed when
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* the Line Control Register is set to 0xBFh.
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*/
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
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/* Turn on RTS flow control, turn off IXOFF flow control */
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isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR);
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isr_fcr &= ~(UART_EXAR654_EFR_IXOFF);
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writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
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/* Write old LCR value back out, which turns enhanced access off */
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writeb(lcrb, &ch->ch_cls_uart->lcr);
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/* Enable interrupts for RTS flow */
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ier |= (UART_EXAR654_IER_RTSDTR);
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writeb(ier, &ch->ch_cls_uart->ier);
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/* Set the usual FIFO values */
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writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
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writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
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UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
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&ch->ch_cls_uart->isr_fcr);
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ch->ch_r_watermark = 4;
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ch->ch_r_tlevel = 8;
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}
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static inline void cls_set_ixoff_flow_control(struct channel_t *ch)
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{
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unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
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unsigned char ier = readb(&ch->ch_cls_uart->ier);
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unsigned char isr_fcr = 0;
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/*
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* The Enhanced Register Set may only be accessed when
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* the Line Control Register is set to 0xBFh.
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*/
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
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/* Turn on IXOFF flow control, turn off RTS flow control */
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isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF);
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isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR);
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writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
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/* Now set our current start/stop chars while in enhanced mode */
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writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
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writeb(0, &ch->ch_cls_uart->lsr);
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writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
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writeb(0, &ch->ch_cls_uart->spr);
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/* Write old LCR value back out, which turns enhanced access off */
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writeb(lcrb, &ch->ch_cls_uart->lcr);
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/* Disable interrupts for RTS flow */
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ier &= ~(UART_EXAR654_IER_RTSDTR);
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writeb(ier, &ch->ch_cls_uart->ier);
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/* Set the usual FIFO values */
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writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
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writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
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UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
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&ch->ch_cls_uart->isr_fcr);
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}
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static inline void cls_set_no_input_flow_control(struct channel_t *ch)
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{
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unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
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unsigned char ier = readb(&ch->ch_cls_uart->ier);
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unsigned char isr_fcr = 0;
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/*
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* The Enhanced Register Set may only be accessed when
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* the Line Control Register is set to 0xBFh.
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*/
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
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/* Turn off IXOFF flow control, turn off RTS flow control */
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isr_fcr |= (UART_EXAR654_EFR_ECB);
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isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF);
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writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
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/* Write old LCR value back out, which turns enhanced access off */
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writeb(lcrb, &ch->ch_cls_uart->lcr);
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/* Disable interrupts for RTS flow */
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ier &= ~(UART_EXAR654_IER_RTSDTR);
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writeb(ier, &ch->ch_cls_uart->ier);
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/* Set the usual FIFO values */
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writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
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writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
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UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
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&ch->ch_cls_uart->isr_fcr);
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ch->ch_t_tlevel = 16;
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ch->ch_r_tlevel = 16;
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}
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/*
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* Determines whether its time to shut off break condition.
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*
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* No locks are assumed to be held when calling this function.
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* channel lock is held and released in this function.
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*/
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static inline void cls_clear_break(struct channel_t *ch, int force)
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{
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unsigned long flags;
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if (!ch)
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return;
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spin_lock_irqsave(&ch->ch_lock, flags);
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if (!ch->ch_stop_sending_break) {
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spin_unlock_irqrestore(&ch->ch_lock, flags);
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return;
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}
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/* Turn break off, and unset some variables */
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if (ch->ch_flags & CH_BREAK_SENDING) {
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if (time_after(jiffies, ch->ch_stop_sending_break) || force) {
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unsigned char temp = readb(&ch->ch_cls_uart->lcr);
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writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
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ch->ch_flags &= ~(CH_BREAK_SENDING);
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ch->ch_stop_sending_break = 0;
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}
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}
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spin_unlock_irqrestore(&ch->ch_lock, flags);
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}
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static void cls_copy_data_from_uart_to_queue(struct channel_t *ch)
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{
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int qleft = 0;
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unsigned char linestatus = 0;
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unsigned char error_mask = 0;
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ushort head;
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ushort tail;
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unsigned long flags;
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if (!ch)
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return;
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spin_lock_irqsave(&ch->ch_lock, flags);
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head = ch->ch_r_head;
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tail = ch->ch_r_tail;
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qleft = tail - head - 1;
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if (qleft < 0)
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qleft += RQUEUEMASK + 1;
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/*
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* Create a mask to determine whether we should
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* insert the character (if any) into our queue.
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*/
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if (ch->ch_c_iflag & IGNBRK)
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error_mask |= UART_LSR_BI;
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while (1) {
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linestatus = readb(&ch->ch_cls_uart->lsr);
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if (!(linestatus & (UART_LSR_DR)))
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break;
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/* Discard character if we are ignoring the error mask. */
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if (linestatus & error_mask) {
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linestatus = 0;
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readb(&ch->ch_cls_uart->txrx);
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continue;
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}
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/*
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* If our queue is full, we have no choice but to drop some
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* data. The assumption is that HWFLOW or SWFLOW should have
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* stopped things way way before we got to this point.
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*/
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while (qleft < 1) {
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tail = (tail + 1) & RQUEUEMASK;
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ch->ch_r_tail = tail;
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ch->ch_err_overrun++;
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qleft++;
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}
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ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE
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| UART_LSR_FE);
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ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);
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qleft--;
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if (ch->ch_equeue[head] & UART_LSR_PE)
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ch->ch_err_parity++;
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if (ch->ch_equeue[head] & UART_LSR_BI)
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ch->ch_err_break++;
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if (ch->ch_equeue[head] & UART_LSR_FE)
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ch->ch_err_frame++;
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head = (head + 1) & RQUEUEMASK;
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ch->ch_rxcount++;
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}
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ch->ch_r_head = head & RQUEUEMASK;
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ch->ch_e_head = head & EQUEUEMASK;
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spin_unlock_irqrestore(&ch->ch_lock, flags);
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}
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/* Make the UART raise any of the output signals we want up */
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static void cls_assert_modem_signals(struct channel_t *ch)
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{
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unsigned char out;
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if (!ch)
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return;
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out = ch->ch_mostat;
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if (ch->ch_flags & CH_LOOPBACK)
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out |= UART_MCR_LOOP;
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writeb(out, &ch->ch_cls_uart->mcr);
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/* Give time for the UART to actually drop the signals */
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usleep_range(10, 20);
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}
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static void cls_copy_data_from_queue_to_uart(struct channel_t *ch)
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{
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ushort head;
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ushort tail;
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int n;
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int qlen;
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uint len_written = 0;
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unsigned long flags;
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if (!ch)
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return;
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spin_lock_irqsave(&ch->ch_lock, flags);
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if (ch->ch_w_tail == ch->ch_w_head)
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goto exit_unlock;
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/* If port is "stopped", don't send any data to the UART */
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if ((ch->ch_flags & CH_FORCED_STOP) ||
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(ch->ch_flags & CH_BREAK_SENDING))
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goto exit_unlock;
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if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
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goto exit_unlock;
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n = 32;
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head = ch->ch_w_head & WQUEUEMASK;
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tail = ch->ch_w_tail & WQUEUEMASK;
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qlen = (head - tail) & WQUEUEMASK;
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n = min(n, qlen);
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while (n > 0) {
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/*
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* If RTS Toggle mode is on, turn on RTS now if not already set,
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* and make sure we get an event when the data transfer has
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* completed.
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*/
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if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
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if (!(ch->ch_mostat & UART_MCR_RTS)) {
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ch->ch_mostat |= (UART_MCR_RTS);
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cls_assert_modem_signals(ch);
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}
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ch->ch_tun.un_flags |= (UN_EMPTY);
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}
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/*
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* If DTR Toggle mode is on, turn on DTR now if not already set,
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* and make sure we get an event when the data transfer has
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* completed.
|
*/
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if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
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if (!(ch->ch_mostat & UART_MCR_DTR)) {
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ch->ch_mostat |= (UART_MCR_DTR);
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cls_assert_modem_signals(ch);
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}
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ch->ch_tun.un_flags |= (UN_EMPTY);
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}
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writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_cls_uart->txrx);
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ch->ch_w_tail++;
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ch->ch_w_tail &= WQUEUEMASK;
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ch->ch_txcount++;
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len_written++;
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n--;
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}
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if (len_written > 0)
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ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
|
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exit_unlock:
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spin_unlock_irqrestore(&ch->ch_lock, flags);
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}
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static void cls_parse_modem(struct channel_t *ch, unsigned char signals)
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{
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unsigned char msignals = signals;
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unsigned long flags;
|
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if (!ch)
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return;
|
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/*
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* Do altpin switching. Altpin switches DCD and DSR.
|
* This prolly breaks DSRPACE, so we should be more clever here.
|
*/
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spin_lock_irqsave(&ch->ch_lock, flags);
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if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
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unsigned char mswap = signals;
|
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if (mswap & UART_MSR_DDCD) {
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msignals &= ~UART_MSR_DDCD;
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msignals |= UART_MSR_DDSR;
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}
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if (mswap & UART_MSR_DDSR) {
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msignals &= ~UART_MSR_DDSR;
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msignals |= UART_MSR_DDCD;
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}
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if (mswap & UART_MSR_DCD) {
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msignals &= ~UART_MSR_DCD;
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msignals |= UART_MSR_DSR;
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}
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if (mswap & UART_MSR_DSR) {
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msignals &= ~UART_MSR_DSR;
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msignals |= UART_MSR_DCD;
|
}
|
}
|
spin_unlock_irqrestore(&ch->ch_lock, flags);
|
|
/* Scrub off lower bits. They signify delta's */
|
signals &= 0xf0;
|
|
spin_lock_irqsave(&ch->ch_lock, flags);
|
if (msignals & UART_MSR_DCD)
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ch->ch_mistat |= UART_MSR_DCD;
|
else
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ch->ch_mistat &= ~UART_MSR_DCD;
|
|
if (msignals & UART_MSR_DSR)
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ch->ch_mistat |= UART_MSR_DSR;
|
else
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ch->ch_mistat &= ~UART_MSR_DSR;
|
|
if (msignals & UART_MSR_RI)
|
ch->ch_mistat |= UART_MSR_RI;
|
else
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ch->ch_mistat &= ~UART_MSR_RI;
|
|
if (msignals & UART_MSR_CTS)
|
ch->ch_mistat |= UART_MSR_CTS;
|
else
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ch->ch_mistat &= ~UART_MSR_CTS;
|
spin_unlock_irqrestore(&ch->ch_lock, flags);
|
}
|
|
/* Parse the ISR register for the specific port */
|
static inline void cls_parse_isr(struct dgnc_board *brd, uint port)
|
{
|
struct channel_t *ch;
|
unsigned char isr = 0;
|
unsigned long flags;
|
|
/*
|
* No need to verify board pointer, it was already
|
* verified in the interrupt routine.
|
*/
|
|
if (port >= brd->nasync)
|
return;
|
|
ch = brd->channels[port];
|
|
/* Here we try to figure out what caused the interrupt to happen */
|
while (1) {
|
isr = readb(&ch->ch_cls_uart->isr_fcr);
|
|
if (isr & UART_IIR_NO_INT)
|
break;
|
|
/* Receive Interrupt pending */
|
if (isr & (UART_IIR_RDI | UART_IIR_RDI_TIMEOUT)) {
|
cls_copy_data_from_uart_to_queue(ch);
|
dgnc_check_queue_flow_control(ch);
|
}
|
|
/* Transmit Hold register empty pending */
|
if (isr & UART_IIR_THRI) {
|
spin_lock_irqsave(&ch->ch_lock, flags);
|
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
|
spin_unlock_irqrestore(&ch->ch_lock, flags);
|
cls_copy_data_from_queue_to_uart(ch);
|
}
|
|
cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
|
}
|
}
|
|
/* Channel lock MUST be held before calling this function! */
|
static void cls_flush_uart_write(struct channel_t *ch)
|
{
|
if (!ch)
|
return;
|
|
writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
|
&ch->ch_cls_uart->isr_fcr);
|
|
/* Must use *delay family functions in atomic context */
|
udelay(10);
|
|
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
|
}
|
|
/* Channel lock MUST be held before calling this function! */
|
static void cls_flush_uart_read(struct channel_t *ch)
|
{
|
if (!ch)
|
return;
|
|
/*
|
* For complete POSIX compatibility, we should be purging the
|
* read FIFO in the UART here.
|
*
|
* However, clearing the read FIFO (UART_FCR_CLEAR_RCVR) also
|
* incorrectly flushes write data as well as just basically trashing the
|
* FIFO.
|
*
|
* Presumably, this is a bug in this UART.
|
*/
|
|
udelay(10);
|
}
|
|
/* Send any/all changes to the line to the UART. */
|
static void cls_param(struct tty_struct *tty)
|
{
|
unsigned char lcr = 0;
|
unsigned char uart_lcr = 0;
|
unsigned char ier = 0;
|
unsigned char uart_ier = 0;
|
uint baud = 9600;
|
int quot = 0;
|
struct dgnc_board *bd;
|
struct channel_t *ch;
|
struct un_t *un;
|
|
if (!tty)
|
return;
|
|
un = (struct un_t *)tty->driver_data;
|
if (!un)
|
return;
|
|
ch = un->un_ch;
|
if (!ch)
|
return;
|
|
bd = ch->ch_bd;
|
if (!bd)
|
return;
|
|
/* If baud rate is zero, flush queues, and set mval to drop DTR. */
|
if ((ch->ch_c_cflag & (CBAUD)) == 0) {
|
ch->ch_r_head = 0;
|
ch->ch_r_tail = 0;
|
ch->ch_e_head = 0;
|
ch->ch_e_tail = 0;
|
ch->ch_w_head = 0;
|
ch->ch_w_tail = 0;
|
|
cls_flush_uart_write(ch);
|
cls_flush_uart_read(ch);
|
|
/* The baudrate is B0 so all modem lines are to be dropped. */
|
ch->ch_flags |= (CH_BAUD0);
|
ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
|
cls_assert_modem_signals(ch);
|
ch->ch_old_baud = 0;
|
return;
|
} else if (ch->ch_custom_speed) {
|
baud = ch->ch_custom_speed;
|
/* Handle transition from B0 */
|
if (ch->ch_flags & CH_BAUD0) {
|
ch->ch_flags &= ~(CH_BAUD0);
|
|
/*
|
* Bring back up RTS and DTR...
|
* Also handle RTS or DTR toggle if set.
|
*/
|
if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
|
ch->ch_mostat |= (UART_MCR_RTS);
|
if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
|
ch->ch_mostat |= (UART_MCR_DTR);
|
}
|
|
} else {
|
int iindex = 0;
|
int jindex = 0;
|
|
ulong bauds[4][16] = {
|
{ /* slowbaud */
|
0, 50, 75, 110,
|
134, 150, 200, 300,
|
600, 1200, 1800, 2400,
|
4800, 9600, 19200, 38400 },
|
{ /* slowbaud & CBAUDEX */
|
0, 57600, 115200, 230400,
|
460800, 150, 200, 921600,
|
600, 1200, 1800, 2400,
|
4800, 9600, 19200, 38400 },
|
{ /* fastbaud */
|
0, 57600, 76800, 115200,
|
131657, 153600, 230400, 460800,
|
921600, 1200, 1800, 2400,
|
4800, 9600, 19200, 38400 },
|
{ /* fastbaud & CBAUDEX */
|
0, 57600, 115200, 230400,
|
460800, 150, 200, 921600,
|
600, 1200, 1800, 2400,
|
4800, 9600, 19200, 38400 }
|
};
|
|
/*
|
* Only use the TXPrint baud rate if the terminal
|
* unit is NOT open
|
*/
|
if (!(ch->ch_tun.un_flags & UN_ISOPEN) &&
|
(un->un_type == DGNC_PRINT))
|
baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
|
else
|
baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
|
|
if (ch->ch_c_cflag & CBAUDEX)
|
iindex = 1;
|
|
if (ch->ch_digi.digi_flags & DIGI_FAST)
|
iindex += 2;
|
|
jindex = baud;
|
|
if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) &&
|
(jindex < 16)) {
|
baud = bauds[iindex][jindex];
|
} else {
|
baud = 0;
|
}
|
|
if (baud == 0)
|
baud = 9600;
|
|
/* Handle transition from B0 */
|
if (ch->ch_flags & CH_BAUD0) {
|
ch->ch_flags &= ~(CH_BAUD0);
|
|
/*
|
* Bring back up RTS and DTR...
|
* Also handle RTS or DTR toggle if set.
|
*/
|
if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
|
ch->ch_mostat |= (UART_MCR_RTS);
|
if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
|
ch->ch_mostat |= (UART_MCR_DTR);
|
}
|
}
|
|
if (ch->ch_c_cflag & PARENB)
|
lcr |= UART_LCR_PARITY;
|
|
if (!(ch->ch_c_cflag & PARODD))
|
lcr |= UART_LCR_EPAR;
|
|
#ifdef CMSPAR
|
if (ch->ch_c_cflag & CMSPAR)
|
lcr |= UART_LCR_SPAR;
|
#endif
|
|
if (ch->ch_c_cflag & CSTOPB)
|
lcr |= UART_LCR_STOP;
|
|
switch (ch->ch_c_cflag & CSIZE) {
|
case CS5:
|
lcr |= UART_LCR_WLEN5;
|
break;
|
case CS6:
|
lcr |= UART_LCR_WLEN6;
|
break;
|
case CS7:
|
lcr |= UART_LCR_WLEN7;
|
break;
|
case CS8:
|
default:
|
lcr |= UART_LCR_WLEN8;
|
break;
|
}
|
|
uart_ier = readb(&ch->ch_cls_uart->ier);
|
ier = uart_ier;
|
uart_lcr = readb(&ch->ch_cls_uart->lcr);
|
|
if (baud == 0)
|
baud = 9600;
|
|
quot = ch->ch_bd->bd_dividend / baud;
|
|
if (quot != 0 && ch->ch_old_baud != baud) {
|
ch->ch_old_baud = baud;
|
writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr);
|
writeb((quot & 0xff), &ch->ch_cls_uart->txrx);
|
writeb((quot >> 8), &ch->ch_cls_uart->ier);
|
writeb(lcr, &ch->ch_cls_uart->lcr);
|
}
|
|
if (uart_lcr != lcr)
|
writeb(lcr, &ch->ch_cls_uart->lcr);
|
|
if (ch->ch_c_cflag & CREAD)
|
ier |= (UART_IER_RDI | UART_IER_RLSI);
|
else
|
ier &= ~(UART_IER_RDI | UART_IER_RLSI);
|
|
/*
|
* Have the UART interrupt on modem signal changes ONLY when
|
* we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
|
*/
|
if ((ch->ch_digi.digi_flags & CTSPACE) ||
|
(ch->ch_digi.digi_flags & RTSPACE) ||
|
(ch->ch_c_cflag & CRTSCTS) ||
|
!(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
|
!(ch->ch_c_cflag & CLOCAL))
|
ier |= UART_IER_MSI;
|
else
|
ier &= ~UART_IER_MSI;
|
|
ier |= UART_IER_THRI;
|
|
if (ier != uart_ier)
|
writeb(ier, &ch->ch_cls_uart->ier);
|
|
if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
|
cls_set_cts_flow_control(ch);
|
} else if (ch->ch_c_iflag & IXON) {
|
if ((ch->ch_startc == _POSIX_VDISABLE) ||
|
(ch->ch_stopc == _POSIX_VDISABLE))
|
cls_set_no_output_flow_control(ch);
|
else
|
cls_set_ixon_flow_control(ch);
|
} else {
|
cls_set_no_output_flow_control(ch);
|
}
|
|
if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
|
cls_set_rts_flow_control(ch);
|
} else if (ch->ch_c_iflag & IXOFF) {
|
if ((ch->ch_startc == _POSIX_VDISABLE) ||
|
(ch->ch_stopc == _POSIX_VDISABLE))
|
cls_set_no_input_flow_control(ch);
|
else
|
cls_set_ixoff_flow_control(ch);
|
} else {
|
cls_set_no_input_flow_control(ch);
|
}
|
|
cls_assert_modem_signals(ch);
|
|
cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
|
}
|
|
/* Board poller function. */
|
static void cls_tasklet(unsigned long data)
|
{
|
struct dgnc_board *bd = (struct dgnc_board *)data;
|
struct channel_t *ch;
|
unsigned long flags;
|
int i;
|
int state = 0;
|
int ports = 0;
|
|
if (!bd)
|
return;
|
|
spin_lock_irqsave(&bd->bd_lock, flags);
|
state = bd->state;
|
ports = bd->nasync;
|
spin_unlock_irqrestore(&bd->bd_lock, flags);
|
|
/*
|
* Do NOT allow the interrupt routine to read the intr registers
|
* Until we release this lock.
|
*/
|
spin_lock_irqsave(&bd->bd_intr_lock, flags);
|
|
if ((state == BOARD_READY) && (ports > 0)) {
|
for (i = 0; i < ports; i++) {
|
ch = bd->channels[i];
|
|
/*
|
* NOTE: Remember you CANNOT hold any channel
|
* locks when calling input.
|
* During input processing, its possible we
|
* will call ld, which might do callbacks back
|
* into us.
|
*/
|
dgnc_input(ch);
|
|
/*
|
* Channel lock is grabbed and then released
|
* inside this routine.
|
*/
|
cls_copy_data_from_queue_to_uart(ch);
|
dgnc_wakeup_writes(ch);
|
|
dgnc_carrier(ch);
|
|
/*
|
* The timing check of turning off the break is done
|
* inside clear_break()
|
*/
|
if (ch->ch_stop_sending_break)
|
cls_clear_break(ch, 0);
|
}
|
}
|
|
spin_unlock_irqrestore(&bd->bd_intr_lock, flags);
|
}
|
|
/* Classic specific interrupt handler. */
|
static irqreturn_t cls_intr(int irq, void *voidbrd)
|
{
|
struct dgnc_board *brd = voidbrd;
|
uint i = 0;
|
unsigned char poll_reg;
|
unsigned long flags;
|
|
if (!brd)
|
return IRQ_NONE;
|
|
spin_lock_irqsave(&brd->bd_intr_lock, flags);
|
|
poll_reg = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET);
|
if (!poll_reg) {
|
spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
|
return IRQ_NONE;
|
}
|
|
for (i = 0; i < brd->nasync; i++)
|
cls_parse_isr(brd, i);
|
|
tasklet_schedule(&brd->helper_tasklet);
|
|
spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
|
|
return IRQ_HANDLED;
|
}
|
|
static void cls_disable_receiver(struct channel_t *ch)
|
{
|
unsigned char tmp = readb(&ch->ch_cls_uart->ier);
|
|
tmp &= ~(UART_IER_RDI);
|
writeb(tmp, &ch->ch_cls_uart->ier);
|
}
|
|
static void cls_enable_receiver(struct channel_t *ch)
|
{
|
unsigned char tmp = readb(&ch->ch_cls_uart->ier);
|
|
tmp |= (UART_IER_RDI);
|
writeb(tmp, &ch->ch_cls_uart->ier);
|
}
|
|
/*
|
* This function basically goes to sleep for seconds, or until
|
* it gets signalled that the port has fully drained.
|
*/
|
static int cls_drain(struct tty_struct *tty, uint seconds)
|
{
|
unsigned long flags;
|
struct channel_t *ch;
|
struct un_t *un;
|
|
if (!tty)
|
return -ENXIO;
|
|
un = (struct un_t *)tty->driver_data;
|
if (!un)
|
return -ENXIO;
|
|
ch = un->un_ch;
|
if (!ch)
|
return -ENXIO;
|
|
spin_lock_irqsave(&ch->ch_lock, flags);
|
un->un_flags |= UN_EMPTY;
|
spin_unlock_irqrestore(&ch->ch_lock, flags);
|
|
/* NOTE: Do something with time passed in. */
|
|
/* If ret is non-zero, user ctrl-c'ed us */
|
|
return wait_event_interruptible(un->un_flags_wait,
|
((un->un_flags & UN_EMPTY) == 0));
|
}
|
|
static void cls_send_start_character(struct channel_t *ch)
|
{
|
if (!ch)
|
return;
|
|
if (ch->ch_startc != _POSIX_VDISABLE) {
|
ch->ch_xon_sends++;
|
writeb(ch->ch_startc, &ch->ch_cls_uart->txrx);
|
}
|
}
|
|
static void cls_send_stop_character(struct channel_t *ch)
|
{
|
if (!ch)
|
return;
|
|
if (ch->ch_stopc != _POSIX_VDISABLE) {
|
ch->ch_xoff_sends++;
|
writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx);
|
}
|
}
|
|
static void cls_uart_init(struct channel_t *ch)
|
{
|
unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
|
unsigned char isr_fcr = 0;
|
|
writeb(0, &ch->ch_cls_uart->ier);
|
|
/*
|
* The Enhanced Register Set may only be accessed when
|
* the Line Control Register is set to 0xBFh.
|
*/
|
writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
|
|
isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
|
|
/* Turn on Enhanced/Extended controls */
|
isr_fcr |= (UART_EXAR654_EFR_ECB);
|
|
writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
|
|
/* Write old LCR value back out, which turns enhanced access off */
|
writeb(lcrb, &ch->ch_cls_uart->lcr);
|
|
/* Clear out UART and FIFO */
|
readb(&ch->ch_cls_uart->txrx);
|
|
writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
|
&ch->ch_cls_uart->isr_fcr);
|
usleep_range(10, 20);
|
|
ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
|
|
readb(&ch->ch_cls_uart->lsr);
|
readb(&ch->ch_cls_uart->msr);
|
}
|
|
static void cls_uart_off(struct channel_t *ch)
|
{
|
writeb(0, &ch->ch_cls_uart->ier);
|
}
|
|
/*
|
* The channel lock MUST be held by the calling function.
|
* Returns 0 is nothing left in the FIFO, returns 1 otherwise.
|
*/
|
static uint cls_get_uart_bytes_left(struct channel_t *ch)
|
{
|
unsigned char left = 0;
|
unsigned char lsr = 0;
|
|
if (!ch)
|
return 0;
|
|
lsr = readb(&ch->ch_cls_uart->lsr);
|
|
/* Determine whether the Transmitter is empty or not */
|
if (!(lsr & UART_LSR_TEMT)) {
|
if (ch->ch_flags & CH_TX_FIFO_EMPTY)
|
tasklet_schedule(&ch->ch_bd->helper_tasklet);
|
left = 1;
|
} else {
|
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
|
left = 0;
|
}
|
|
return left;
|
}
|
|
/*
|
* Starts sending a break thru the UART.
|
* The channel lock MUST be held by the calling function.
|
*/
|
static void cls_send_break(struct channel_t *ch, int msecs)
|
{
|
if (!ch)
|
return;
|
|
/* If we receive a time of 0, this means turn off the break. */
|
if (msecs == 0) {
|
if (ch->ch_flags & CH_BREAK_SENDING) {
|
unsigned char temp = readb(&ch->ch_cls_uart->lcr);
|
|
writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
|
ch->ch_flags &= ~(CH_BREAK_SENDING);
|
ch->ch_stop_sending_break = 0;
|
}
|
return;
|
}
|
|
/*
|
* Set the time we should stop sending the break.
|
* If we are already sending a break, toss away the existing
|
* time to stop, and use this new value instead.
|
*/
|
ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
|
|
/* Tell the UART to start sending the break */
|
if (!(ch->ch_flags & CH_BREAK_SENDING)) {
|
unsigned char temp = readb(&ch->ch_cls_uart->lcr);
|
|
writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr);
|
ch->ch_flags |= (CH_BREAK_SENDING);
|
}
|
}
|
|
/*
|
* Sends a specific character as soon as possible to the UART,
|
* jumping over any bytes that might be in the write queue.
|
*
|
* The channel lock MUST be held by the calling function.
|
*/
|
static void cls_send_immediate_char(struct channel_t *ch, unsigned char c)
|
{
|
if (!ch)
|
return;
|
|
writeb(c, &ch->ch_cls_uart->txrx);
|
}
|
|
struct board_ops dgnc_cls_ops = {
|
.tasklet = cls_tasklet,
|
.intr = cls_intr,
|
.uart_init = cls_uart_init,
|
.uart_off = cls_uart_off,
|
.drain = cls_drain,
|
.param = cls_param,
|
.assert_modem_signals = cls_assert_modem_signals,
|
.flush_uart_write = cls_flush_uart_write,
|
.flush_uart_read = cls_flush_uart_read,
|
.disable_receiver = cls_disable_receiver,
|
.enable_receiver = cls_enable_receiver,
|
.send_break = cls_send_break,
|
.send_start_character = cls_send_start_character,
|
.send_stop_character = cls_send_stop_character,
|
.copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart,
|
.get_uart_bytes_left = cls_get_uart_bytes_left,
|
.send_immediate_char = cls_send_immediate_char
|
};
|
