// SPDX-License-Identifier: GPL-2.0
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/*
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* Rockchip PCIE3.0 phy driver
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*
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* Copyright (C) 2020 Rockchip Electronics Co., Ltd.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <dt-bindings/phy/phy.h>
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#define GRF_PCIE30PHY_CON1 0x4
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#define GRF_PCIE30PHY_CON4 0x10
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#define GRF_PCIE30PHY_CON6 0x18
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#define GRF_PCIE30PHY_CON9 0x24
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#define GRF_PCIE30PHY_STATUS0 0x80
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#define SRAM_INIT_DONE(reg) (reg & BIT(14))
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struct rockchip_p3phy_priv {
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void __iomem *mmio;
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int mode;
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struct regmap *phy_grf;
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struct reset_control *p30phy;
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struct clk *ref_clk_m;
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struct clk *ref_clk_n;
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struct clk *pclk;
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struct phy *phy;
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bool is_bifurcation;
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};
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static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode)
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{
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struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
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/* Acutally We don't care EP/RC mode, but just record it */
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switch (mode) {
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case PHY_MODE_PCIE_RC:
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priv->mode = PHY_MODE_PCIE_RC;
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break;
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case PHY_MODE_PCIE_EP:
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priv->mode = PHY_MODE_PCIE_EP;
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break;
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case PHY_MODE_PCIE_BIFURCATION:
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priv->is_bifurcation = true;
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break;
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default:
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pr_info("%s, invalid mode\n", __func__);
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return -EINVAL;
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}
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return 0;
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}
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static const u16 phy_fw[] = {
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#include "phy-rockchip-snps-pcie3.fw"
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};
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static int rochchip_p3phy_init(struct phy *phy)
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{
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struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
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int i;
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int ret = 0;
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u32 reg;
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ret = clk_prepare_enable(priv->ref_clk_m);
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if (ret < 0)
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return ret;
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ret = clk_prepare_enable(priv->ref_clk_n);
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if (ret < 0)
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goto err_ref;
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ret = clk_prepare_enable(priv->pclk);
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if (ret < 0)
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goto err_pclk;
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reset_control_assert(priv->p30phy);
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udelay(1);
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/* Deassert PCIe PMA output clamp mode */
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
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(0x1 << 15) | (0x1 << 31));
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/* Set bifurcation if needed, and it doesn't care RC/EP */
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if (priv->is_bifurcation) {
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
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0x1 | (0xf << 16));
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,
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(0x1 << 15) | (0x1 << 31));
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}
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
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(0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
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(0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass
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reset_control_deassert(priv->p30phy);
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ret = regmap_read_poll_timeout(priv->phy_grf,
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GRF_PCIE30PHY_STATUS0,
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reg, SRAM_INIT_DONE(reg),
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0, 500);
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if (ret) {
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pr_err("%s: lock failed 0x%x, check input refclk and power supply\n",
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__func__, reg);
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goto err_pclk;
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}
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
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(0x3 << 8) | (0x3 << (8 + 16))); //map to access sram
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for (i = 0; i < ARRAY_SIZE(phy_fw); i++)
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writel(phy_fw[i], priv->mmio + (i<<2));
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pr_info("snps pcie3phy FW update! size %ld\n", ARRAY_SIZE(phy_fw));
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
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(0x0 << 8) | (0x3 << (8 + 16)));
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
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(0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
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return 0;
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err_pclk:
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clk_disable_unprepare(priv->ref_clk_n);
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err_ref:
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clk_disable_unprepare(priv->ref_clk_m);
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return ret;
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}
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static int rochchip_p3phy_exit(struct phy *phy)
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{
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struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
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clk_disable_unprepare(priv->ref_clk_m);
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clk_disable_unprepare(priv->ref_clk_n);
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clk_disable_unprepare(priv->pclk);
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reset_control_assert(priv->p30phy);
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return 0;
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}
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static const struct phy_ops rochchip_p3phy_ops = {
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.init = rochchip_p3phy_init,
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.exit = rochchip_p3phy_exit,
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.set_mode = rockchip_p3phy_set_mode,
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.owner = THIS_MODULE,
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};
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static int rockchip_p3phy_probe(struct platform_device *pdev)
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{
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struct phy_provider *phy_provider;
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struct device *dev = &pdev->dev;
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struct rockchip_p3phy_priv *priv;
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struct device_node *np = dev->of_node;
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struct resource *res;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->mmio = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->mmio)) {
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ret = PTR_ERR(priv->mmio);
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return ret;
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}
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priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf");
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if (IS_ERR(priv->phy_grf)) {
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dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
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return PTR_ERR(priv->phy_grf);
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}
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priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops);
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if (IS_ERR(priv->phy)) {
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dev_err(dev, "failed to create combphy\n");
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return PTR_ERR(priv->phy);
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}
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priv->p30phy = devm_reset_control_get(dev, "phy");
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if (IS_ERR(priv->p30phy)) {
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dev_warn(dev, "no phy reset control specified\n");
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priv->p30phy = NULL;
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}
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priv->ref_clk_m = devm_clk_get(dev, "refclk_m");
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if (IS_ERR(priv->ref_clk_m)) {
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dev_err(dev, "failed to find ref clock M\n");
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return PTR_ERR(priv->ref_clk_m);
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}
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priv->ref_clk_n = devm_clk_get(dev, "refclk_n");
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if (IS_ERR(priv->ref_clk_n)) {
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dev_err(dev, "failed to find ref clock N\n");
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return PTR_ERR(priv->ref_clk_n);
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}
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priv->pclk = devm_clk_get(dev, "pclk");
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if (IS_ERR(priv->pclk)) {
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dev_err(dev, "failed to find pclk\n");
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return PTR_ERR(priv->pclk);
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}
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dev_set_drvdata(dev, priv);
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phy_set_drvdata(priv->phy, priv);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct of_device_id rockchip_p3phy_of_match[] = {
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{ .compatible = "rockchip,rk3568-pcie3-phy" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match);
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static struct platform_driver rockchip_p3phy_driver = {
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.probe = rockchip_p3phy_probe,
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.driver = {
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.name = "rockchip-snps-pcie3-phy",
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.of_match_table = rockchip_p3phy_of_match,
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},
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};
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module_platform_driver(rockchip_p3phy_driver);
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MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver");
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MODULE_LICENSE("GPL v2");
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