// SPDX-License-Identifier: GPL-2.0
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/*
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* Rockchip MIPI CSI2 DPHY driver
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*
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* Copyright (C) 2021 Rockchip Electronics Co., Ltd.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_graph.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <media/media-entity.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-fwnode.h>
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#include <media/v4l2-subdev.h>
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#include <media/v4l2-device.h>
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#include "phy-rockchip-csi2-dphy-common.h"
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/* GRF REG OFFSET */
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#define GRF_VI_CON0 (0x0340)
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#define GRF_VI_CON1 (0x0344)
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/*GRF REG BIT DEFINE */
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#define GRF_CSI2PHY_LANE_SEL_SPLIT (0x1)
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#define GRF_CSI2PHY_SEL_SPLIT_0_1 (0x0)
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#define GRF_CSI2PHY_SEL_SPLIT_2_3 BIT(0)
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/* PHY REG OFFSET */
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#define CSI2_DPHY_CTRL_INVALID_OFFSET (0xffff)
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#define CSI2_DPHY_CTRL_PWRCTL \
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CSI2_DPHY_CTRL_INVALID_OFFSET
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#define CSI2_DPHY_CTRL_LANE_ENABLE (0x00)
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#define CSI2_DPHY_DUAL_CAL_EN (0x80)
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#define CSI2_DPHY_CLK_WR_THS_SETTLE (0x160)
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#define CSI2_DPHY_CLK_CALIB_EN (0x168)
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#define CSI2_DPHY_LANE0_WR_THS_SETTLE (0x1e0)
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#define CSI2_DPHY_LANE0_CALIB_EN (0x1e8)
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#define CSI2_DPHY_LANE1_WR_THS_SETTLE (0x260)
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#define CSI2_DPHY_LANE1_CALIB_EN (0x268)
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#define CSI2_DPHY_LANE2_WR_THS_SETTLE (0x2e0)
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#define CSI2_DPHY_LANE2_CALIB_EN (0x2e8)
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#define CSI2_DPHY_LANE3_WR_THS_SETTLE (0x360)
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#define CSI2_DPHY_LANE3_CALIB_EN (0x368)
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#define CSI2_DPHY_CLK1_WR_THS_SETTLE (0x3e0)
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#define CSI2_DPHY_CLK1_CALIB_EN (0x3e8)
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/* PHY REG BIT DEFINE */
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#define CSI2_DPHY_LANE_MODE_FULL (0x4)
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#define CSI2_DPHY_LANE_MODE_SPLIT (0x2)
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#define CSI2_DPHY_LANE_SPLIT_TOP (0x1)
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#define CSI2_DPHY_LANE_SPLIT_BOT (0x2)
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#define CSI2_DPHY_LANE_SPLIT_LANE0_1 (0x3 << 2)
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#define CSI2_DPHY_LANE_SPLIT_LANE2_3 (0x3 << 4)
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#define CSI2_DPHY_LANE_DUAL_MODE_EN BIT(6)
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#define CSI2_DPHY_LANE_PARA_ARR_NUM (0x2)
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#define CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT 2
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#define CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT 4
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#define CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT 6
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enum csi2_dphy_index {
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DPHY0 = 0x0,
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DPHY1,
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DPHY2,
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};
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enum csi2_dphy_lane {
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CSI2_DPHY_LANE_CLOCK = 0,
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CSI2_DPHY_LANE_CLOCK1,
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CSI2_DPHY_LANE_DATA0,
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CSI2_DPHY_LANE_DATA1,
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CSI2_DPHY_LANE_DATA2,
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CSI2_DPHY_LANE_DATA3
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};
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enum grf_reg_id {
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GRF_DPHY_RX0_TURNDISABLE = 0,
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GRF_DPHY_RX0_FORCERXMODE,
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GRF_DPHY_RX0_FORCETXSTOPMODE,
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GRF_DPHY_RX0_ENABLE,
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GRF_DPHY_RX0_TESTCLR,
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GRF_DPHY_RX0_TESTCLK,
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GRF_DPHY_RX0_TESTEN,
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GRF_DPHY_RX0_TESTDIN,
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GRF_DPHY_RX0_TURNREQUEST,
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GRF_DPHY_RX0_TESTDOUT,
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GRF_DPHY_TX0_TURNDISABLE,
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GRF_DPHY_TX0_FORCERXMODE,
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GRF_DPHY_TX0_FORCETXSTOPMODE,
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GRF_DPHY_TX0_TURNREQUEST,
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GRF_DPHY_TX1RX1_TURNDISABLE,
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GRF_DPHY_TX1RX1_FORCERXMODE,
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GRF_DPHY_TX1RX1_FORCETXSTOPMODE,
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GRF_DPHY_TX1RX1_ENABLE,
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GRF_DPHY_TX1RX1_MASTERSLAVEZ,
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GRF_DPHY_TX1RX1_BASEDIR,
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GRF_DPHY_TX1RX1_ENABLECLK,
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GRF_DPHY_TX1RX1_TURNREQUEST,
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GRF_DPHY_RX1_SRC_SEL,
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/* rk3288 only */
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GRF_CON_DISABLE_ISP,
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GRF_CON_ISP_DPHY_SEL,
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GRF_DSI_CSI_TESTBUS_SEL,
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GRF_DVP_V18SEL,
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/* rk1808 & rk3326 & rv1126 */
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GRF_DPHY_CSI2PHY_FORCERXMODE,
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GRF_DPHY_CSI2PHY_CLKLANE_EN,
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GRF_DPHY_CSI2PHY_DATALANE_EN,
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/* rv1126 only */
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GRF_DPHY_CLK_INV_SEL,
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GRF_DPHY_SEL,
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/* rk3368 only */
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GRF_ISP_MIPI_CSI_HOST_SEL,
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/* below is for rk3399 only */
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GRF_DPHY_RX0_CLK_INV_SEL,
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GRF_DPHY_RX1_CLK_INV_SEL,
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GRF_DPHY_TX1RX1_SRC_SEL,
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/* below is for rk3568 only */
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GRF_DPHY_CSI2PHY_CLKLANE1_EN,
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GRF_DPHY_CLK1_INV_SEL,
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GRF_DPHY_ISP_CSI2PHY_SEL,
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GRF_DPHY_CIF_CSI2PHY_SEL,
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GRF_DPHY_CSI2PHY_LANE_SEL,
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GRF_DPHY_CSI2PHY_DATALANE_EN0,
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GRF_DPHY_CSI2PHY_DATALANE_EN1,
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};
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enum csi2dphy_reg_id {
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CSI2PHY_REG_CTRL_LANE_ENABLE = 0,
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CSI2PHY_CTRL_PWRCTL,
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CSI2PHY_CTRL_DIG_RST,
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CSI2PHY_CLK_THS_SETTLE,
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CSI2PHY_LANE0_THS_SETTLE,
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CSI2PHY_LANE1_THS_SETTLE,
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CSI2PHY_LANE2_THS_SETTLE,
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CSI2PHY_LANE3_THS_SETTLE,
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CSI2PHY_CLK_CALIB_ENABLE,
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CSI2PHY_LANE0_CALIB_ENABLE,
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CSI2PHY_LANE1_CALIB_ENABLE,
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CSI2PHY_LANE2_CALIB_ENABLE,
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CSI2PHY_LANE3_CALIB_ENABLE,
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//rv1126 only
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CSI2PHY_MIPI_LVDS_MODEL,
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CSI2PHY_LVDS_MODE,
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//rk3568 only
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CSI2PHY_DUAL_CLK_EN,
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CSI2PHY_CLK1_THS_SETTLE,
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CSI2PHY_CLK1_CALIB_ENABLE
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};
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#define HIWORD_UPDATE(val, mask, shift) \
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((val) << (shift) | (mask) << ((shift) + 16))
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#define GRF_REG(_offset, _width, _shift) \
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{ .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
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#define CSI2PHY_REG(_offset) \
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{ .offset = _offset, }
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struct hsfreq_range {
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u32 range_h;
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u8 cfg_bit;
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};
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static inline void write_grf_reg(struct csi2_dphy_hw *hw,
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int index, u8 value)
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{
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const struct grf_reg *reg = &hw->grf_regs[index];
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unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
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if (reg->offset)
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regmap_write(hw->regmap_grf, reg->offset, val);
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}
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static inline u32 read_grf_reg(struct csi2_dphy_hw *hw, int index)
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{
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const struct grf_reg *reg = &hw->grf_regs[index];
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unsigned int val = 0;
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if (reg->offset) {
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regmap_read(hw->regmap_grf, reg->offset, &val);
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val = (val >> reg->shift) & reg->mask;
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}
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return val;
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}
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static inline void write_csi2_dphy_reg(struct csi2_dphy_hw *hw,
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int index, u32 value)
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{
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const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
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if ((index == CSI2PHY_REG_CTRL_LANE_ENABLE) ||
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(index != CSI2PHY_REG_CTRL_LANE_ENABLE &&
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reg->offset != 0x0))
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writel(value, hw->hw_base_addr + reg->offset);
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}
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static inline void read_csi2_dphy_reg(struct csi2_dphy_hw *hw,
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int index, u32 *value)
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{
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const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
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if ((index == CSI2PHY_REG_CTRL_LANE_ENABLE) ||
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(index != CSI2PHY_REG_CTRL_LANE_ENABLE &&
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reg->offset != 0x0))
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*value = readl(hw->hw_base_addr + reg->offset);
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}
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static void csi_mipidphy_wr_ths_settle(struct csi2_dphy_hw *hw,
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int hsfreq,
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enum csi2_dphy_lane lane)
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{
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unsigned int val = 0;
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unsigned int offset;
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switch (lane) {
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case CSI2_DPHY_LANE_CLOCK:
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offset = CSI2PHY_CLK_THS_SETTLE;
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break;
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case CSI2_DPHY_LANE_CLOCK1:
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offset = CSI2PHY_CLK1_THS_SETTLE;
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break;
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case CSI2_DPHY_LANE_DATA0:
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offset = CSI2PHY_LANE0_THS_SETTLE;
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break;
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case CSI2_DPHY_LANE_DATA1:
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offset = CSI2PHY_LANE1_THS_SETTLE;
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break;
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case CSI2_DPHY_LANE_DATA2:
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offset = CSI2PHY_LANE2_THS_SETTLE;
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break;
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case CSI2_DPHY_LANE_DATA3:
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offset = CSI2PHY_LANE3_THS_SETTLE;
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break;
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default:
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return;
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}
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read_csi2_dphy_reg(hw, offset, &val);
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val = (val & ~0x7f) | hsfreq;
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write_csi2_dphy_reg(hw, offset, val);
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}
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static const struct grf_reg rk3568_grf_dphy_regs[] = {
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[GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_VI_CON0, 4, 0),
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[GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_VI_CON0, 4, 4),
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[GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(GRF_VI_CON0, 2, 4),
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[GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(GRF_VI_CON0, 2, 6),
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[GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_VI_CON0, 1, 8),
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[GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_VI_CON0, 1, 9),
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[GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_VI_CON0, 1, 10),
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[GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_VI_CON0, 1, 11),
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[GRF_DPHY_ISP_CSI2PHY_SEL] = GRF_REG(GRF_VI_CON1, 1, 12),
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[GRF_DPHY_CIF_CSI2PHY_SEL] = GRF_REG(GRF_VI_CON1, 1, 11),
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[GRF_DPHY_CSI2PHY_LANE_SEL] = GRF_REG(GRF_VI_CON1, 1, 7),
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};
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static const struct csi2dphy_reg rk3568_csi2dphy_regs[] = {
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[CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
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[CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
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[CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
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[CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
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[CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
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[CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
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[CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
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[CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
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[CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
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[CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
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[CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
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[CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
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[CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
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[CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
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};
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static const struct clk_bulk_data rk3568_csi2_dphy_hw_clks[] = {
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{ .id = "pclk" },
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};
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/* These tables must be sorted by .range_h ascending. */
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static const struct hsfreq_range rk3568_csi2_dphy_hw_hsfreq_ranges[] = {
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{ 109, 0x02}, { 149, 0x03}, { 199, 0x06}, { 249, 0x06},
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{ 299, 0x06}, { 399, 0x08}, { 499, 0x0b}, { 599, 0x0e},
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{ 699, 0x10}, { 799, 0x12}, { 999, 0x16}, {1199, 0x1e},
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{1399, 0x23}, {1599, 0x2d}, {1799, 0x32}, {1999, 0x37},
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{2199, 0x3c}, {2399, 0x41}, {2499, 0x46}
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};
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static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd)
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{
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struct media_pad *local, *remote;
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struct media_entity *sensor_me;
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local = &sd->entity.pads[CSI2_DPHY_RX_PAD_SINK];
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remote = media_entity_remote_pad(local);
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if (!remote) {
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v4l2_warn(sd, "No link between dphy and sensor\n");
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return NULL;
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}
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sensor_me = media_entity_remote_pad(local)->entity;
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return media_entity_to_v4l2_subdev(sensor_me);
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}
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static struct csi2_sensor *sd_to_sensor(struct csi2_dphy *dphy,
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struct v4l2_subdev *sd)
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{
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int i;
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for (i = 0; i < dphy->num_sensors; ++i)
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if (dphy->sensors[i].sd == sd)
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return &dphy->sensors[i];
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return NULL;
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}
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static void csi2_dphy_config_dual_mode(struct csi2_dphy *dphy,
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struct csi2_sensor *sensor)
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{
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struct csi2_dphy_hw *hw = dphy->dphy_hw;
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struct v4l2_subdev *sd = &dphy->sd;
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bool is_cif = false;
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char *model;
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u32 val;
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model = sd->v4l2_dev->mdev->model;
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if (!strncmp(model, "rkcif_mipi_lvds", sizeof("rkcif_mipi_lvds") - 1))
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is_cif = true;
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else
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is_cif = false;
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if (hw->lane_mode == LANE_MODE_FULL) {
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val = ~GRF_CSI2PHY_LANE_SEL_SPLIT;
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write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
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write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN,
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GENMASK(sensor->lanes - 1, 0));
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write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
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} else {
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val = GRF_CSI2PHY_LANE_SEL_SPLIT;
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write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
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if (dphy->phy_index == DPHY1) {
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write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0,
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GENMASK(sensor->lanes - 1, 0));
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write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
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if (is_cif)
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write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL,
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GRF_CSI2PHY_SEL_SPLIT_0_1);
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else
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write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL,
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GRF_CSI2PHY_SEL_SPLIT_0_1);
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}
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if (dphy->phy_index == DPHY2) {
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write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1,
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GENMASK(sensor->lanes - 1, 0));
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write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE1_EN, 0x1);
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if (is_cif)
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write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL,
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GRF_CSI2PHY_SEL_SPLIT_2_3);
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else
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write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL,
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GRF_CSI2PHY_SEL_SPLIT_2_3);
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}
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}
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}
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static int csi2_dphy_hw_stream_on(struct csi2_dphy *dphy,
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struct v4l2_subdev *sd)
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{
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struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
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struct csi2_sensor *sensor = sd_to_sensor(dphy, sensor_sd);
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struct csi2_dphy_hw *hw = dphy->dphy_hw;
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const struct dphy_hw_drv_data *drv_data = hw->drv_data;
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const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
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int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
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int i, hsfreq = 0;
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u32 val = 0, pre_val;
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mutex_lock(&hw->mutex);
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/* set data lane num and enable clock lane */
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/*
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* for rk356x: dphy0 is used just for full mode,
|
* dphy1 is used just for split mode,uses lane0_1,
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* dphy2 is used just for split mode,uses lane2_3
|
*/
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read_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, &pre_val);
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if (hw->lane_mode == LANE_MODE_FULL) {
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val |= (GENMASK(sensor->lanes - 1, 0) <<
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CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) |
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(0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
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} else {
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if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT)))
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val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
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if (dphy->phy_index == DPHY1)
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val |= (GENMASK(sensor->lanes - 1, 0) <<
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CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT);
|
|
if (dphy->phy_index == DPHY2)
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val |= (GENMASK(sensor->lanes - 1, 0) <<
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CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT);
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}
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val |= pre_val;
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write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, val);
|
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if (sensor->mbus.type == V4L2_MBUS_CSI2) {
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/* Reset dphy digital part */
|
if (hw->lane_mode == LANE_MODE_FULL) {
|
write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1e);
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write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1f);
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} else {
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read_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, &val);
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if (!(val & CSI2_DPHY_LANE_DUAL_MODE_EN)) {
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write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5e);
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write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5f);
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}
|
}
|
csi2_dphy_config_dual_mode(dphy, sensor);
|
}
|
|
/* not into receive mode/wait stopstate */
|
write_grf_reg(hw, GRF_DPHY_CSI2PHY_FORCERXMODE, 0x0);
|
|
/* enable calibration */
|
if (dphy->data_rate_mbps > 1500) {
|
if (hw->lane_mode == LANE_MODE_FULL) {
|
write_csi2_dphy_reg(hw, CSI2PHY_CLK_CALIB_ENABLE, 0x80);
|
if (sensor->lanes > 0x00)
|
write_csi2_dphy_reg(hw, CSI2PHY_LANE0_CALIB_ENABLE, 0x80);
|
if (sensor->lanes > 0x01)
|
write_csi2_dphy_reg(hw, CSI2PHY_LANE1_CALIB_ENABLE, 0x80);
|
if (sensor->lanes > 0x02)
|
write_csi2_dphy_reg(hw, CSI2PHY_LANE2_CALIB_ENABLE, 0x80);
|
if (sensor->lanes > 0x03)
|
write_csi2_dphy_reg(hw, CSI2PHY_LANE3_CALIB_ENABLE, 0x80);
|
} else {
|
if (dphy->phy_index == DPHY1) {
|
write_csi2_dphy_reg(hw, CSI2PHY_CLK_CALIB_ENABLE, 0x80);
|
if (sensor->lanes > 0x00)
|
write_csi2_dphy_reg(hw, CSI2PHY_LANE0_CALIB_ENABLE, 0x80);
|
if (sensor->lanes > 0x01)
|
write_csi2_dphy_reg(hw, CSI2PHY_LANE1_CALIB_ENABLE, 0x80);
|
}
|
|
if (dphy->phy_index == DPHY2) {
|
write_csi2_dphy_reg(hw, CSI2PHY_CLK1_CALIB_ENABLE, 0x80);
|
if (sensor->lanes > 0x00)
|
write_csi2_dphy_reg(hw, CSI2PHY_LANE2_CALIB_ENABLE, 0x80);
|
if (sensor->lanes > 0x01)
|
write_csi2_dphy_reg(hw, CSI2PHY_LANE3_CALIB_ENABLE, 0x80);
|
}
|
}
|
}
|
|
/* set clock lane and data lane */
|
for (i = 0; i < num_hsfreq_ranges; i++) {
|
if (hsfreq_ranges[i].range_h >= dphy->data_rate_mbps) {
|
hsfreq = hsfreq_ranges[i].cfg_bit;
|
break;
|
}
|
}
|
|
if (i == num_hsfreq_ranges) {
|
i = num_hsfreq_ranges - 1;
|
dev_warn(dphy->dev, "data rate: %lld mbps, max support %d mbps",
|
dphy->data_rate_mbps, hsfreq_ranges[i].range_h + 1);
|
hsfreq = hsfreq_ranges[i].cfg_bit;
|
}
|
|
if (hw->lane_mode == LANE_MODE_FULL) {
|
csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK);
|
if (sensor->lanes > 0x00)
|
csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA0);
|
if (sensor->lanes > 0x01)
|
csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA1);
|
if (sensor->lanes > 0x02)
|
csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA2);
|
if (sensor->lanes > 0x03)
|
csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA3);
|
} else {
|
if (dphy->phy_index == DPHY1) {
|
csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK);
|
csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA0);
|
csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA1);
|
}
|
|
if (dphy->phy_index == DPHY2) {
|
csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK1);
|
csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA2);
|
csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA3);
|
}
|
}
|
|
atomic_inc(&hw->stream_cnt);
|
|
mutex_unlock(&hw->mutex);
|
|
return 0;
|
}
|
|
static int csi2_dphy_hw_stream_off(struct csi2_dphy *dphy,
|
struct v4l2_subdev *sd)
|
{
|
struct csi2_dphy_hw *hw = dphy->dphy_hw;
|
|
if (atomic_dec_return(&hw->stream_cnt))
|
return 0;
|
|
mutex_lock(&hw->mutex);
|
|
write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, 0x01);
|
usleep_range(500, 1000);
|
|
mutex_unlock(&hw->mutex);
|
|
return 0;
|
}
|
|
static void rk3568_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
|
{
|
hw->grf_regs = rk3568_grf_dphy_regs;
|
}
|
|
static const struct dphy_hw_drv_data rk3568_csi2_dphy_hw_drv_data = {
|
.clks = rk3568_csi2_dphy_hw_clks,
|
.num_clks = ARRAY_SIZE(rk3568_csi2_dphy_hw_clks),
|
.hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
|
.num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
|
.csi2dphy_regs = rk3568_csi2dphy_regs,
|
.grf_regs = rk3568_grf_dphy_regs,
|
.individual_init = rk3568_csi2_dphy_hw_individual_init,
|
.chip_id = CHIP_ID_RK3568,
|
};
|
|
static const struct of_device_id rockchip_csi2_dphy_hw_match_id[] = {
|
{
|
.compatible = "rockchip,rk3568-csi2-dphy-hw",
|
.data = &rk3568_csi2_dphy_hw_drv_data,
|
},
|
{}
|
};
|
MODULE_DEVICE_TABLE(of, rockchip_csi2_dphy_hw_match_id);
|
|
static int rockchip_csi2_dphy_hw_probe(struct platform_device *pdev)
|
{
|
struct device *dev = &pdev->dev;
|
struct csi2_dphy_hw *dphy_hw;
|
struct regmap *grf;
|
struct resource *res;
|
const struct of_device_id *of_id;
|
const struct dphy_hw_drv_data *drv_data;
|
int ret;
|
|
dphy_hw = devm_kzalloc(dev, sizeof(*dphy_hw), GFP_KERNEL);
|
if (!dphy_hw)
|
return -ENOMEM;
|
dphy_hw->dev = dev;
|
|
of_id = of_match_device(rockchip_csi2_dphy_hw_match_id, dev);
|
if (!of_id)
|
return -EINVAL;
|
|
grf = syscon_node_to_regmap(dev->parent->of_node);
|
if (IS_ERR(grf)) {
|
grf = syscon_regmap_lookup_by_phandle(dev->of_node,
|
"rockchip,grf");
|
if (IS_ERR(grf)) {
|
dev_err(dev, "Can't find GRF syscon\n");
|
return -ENODEV;
|
}
|
}
|
dphy_hw->regmap_grf = grf;
|
|
drv_data = of_id->data;
|
dphy_hw->num_clks = drv_data->num_clks;
|
dphy_hw->clks = devm_kmemdup(dev, drv_data->clks,
|
drv_data->num_clks * sizeof(struct clk_bulk_data),
|
GFP_KERNEL);
|
if (!dphy_hw->clks) {
|
dev_err(dev, "failed to acquire csi2 dphy clks mem\n");
|
return -ENOMEM;
|
}
|
ret = devm_clk_bulk_get(dev, dphy_hw->num_clks, dphy_hw->clks);
|
if (ret == -EPROBE_DEFER) {
|
dev_err(dev, "get csi2 dphy clks failed\n");
|
return -EPROBE_DEFER;
|
}
|
if (ret)
|
dphy_hw->num_clks = 0;
|
|
dphy_hw->dphy_dev_num = 0;
|
dphy_hw->drv_data = drv_data;
|
dphy_hw->lane_mode = LANE_MODE_UNDEF;
|
dphy_hw->grf_regs = drv_data->grf_regs;
|
dphy_hw->txrx_regs = drv_data->txrx_regs;
|
dphy_hw->csi2dphy_regs = drv_data->csi2dphy_regs;
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
dphy_hw->hw_base_addr = devm_ioremap_resource(dev, res);
|
if (IS_ERR(dphy_hw->hw_base_addr)) {
|
resource_size_t offset = res->start;
|
resource_size_t size = resource_size(res);
|
|
dphy_hw->hw_base_addr = devm_ioremap(dev, offset, size);
|
if (IS_ERR(dphy_hw->hw_base_addr)) {
|
dev_err(dev, "Can't find csi2 dphy hw addr!\n");
|
return -ENODEV;
|
}
|
}
|
dphy_hw->stream_on = csi2_dphy_hw_stream_on;
|
dphy_hw->stream_off = csi2_dphy_hw_stream_off;
|
|
atomic_set(&dphy_hw->stream_cnt, 0);
|
|
mutex_init(&dphy_hw->mutex);
|
|
platform_set_drvdata(pdev, dphy_hw);
|
|
pm_runtime_enable(&pdev->dev);
|
|
platform_driver_register(&rockchip_csi2_dphy_driver);
|
|
dev_info(dev, "csi2 dphy hw probe successfully!\n");
|
|
return 0;
|
}
|
|
static int rockchip_csi2_dphy_hw_remove(struct platform_device *pdev)
|
{
|
struct csi2_dphy_hw *hw = platform_get_drvdata(pdev);
|
|
pm_runtime_disable(&pdev->dev);
|
mutex_destroy(&hw->mutex);
|
|
return 0;
|
}
|
|
static struct platform_driver rockchip_csi2_dphy_hw_driver = {
|
.probe = rockchip_csi2_dphy_hw_probe,
|
.remove = rockchip_csi2_dphy_hw_remove,
|
.driver = {
|
.name = "rockchip-csi2-dphy-hw",
|
.of_match_table = rockchip_csi2_dphy_hw_match_id,
|
},
|
};
|
module_platform_driver(rockchip_csi2_dphy_hw_driver);
|
|
MODULE_AUTHOR("Rockchip Camera/ISP team");
|
MODULE_DESCRIPTION("Rockchip MIPI CSI2 DPHY HW driver");
|
MODULE_LICENSE("GPL v2");
|
