/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Micrel KS8695 (Centaur) Ethernet.
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*
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* Copyright 2008 Simtec Electronics
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* Daniel Silverstone <dsilvers@simtec.co.uk>
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* Vincent Sanders <vince@simtec.co.uk>
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*/
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#ifndef KS8695NET_H
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#define KS8695NET_H
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/* Receive descriptor flags */
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#define RDES_OWN (1 << 31) /* Ownership */
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#define RDES_FS (1 << 30) /* First Descriptor */
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#define RDES_LS (1 << 29) /* Last Descriptor */
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#define RDES_IPE (1 << 28) /* IP Checksum error */
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#define RDES_TCPE (1 << 27) /* TCP Checksum error */
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#define RDES_UDPE (1 << 26) /* UDP Checksum error */
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#define RDES_ES (1 << 25) /* Error summary */
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#define RDES_MF (1 << 24) /* Multicast Frame */
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#define RDES_RE (1 << 19) /* MII Error reported */
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#define RDES_TL (1 << 18) /* Frame too Long */
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#define RDES_RF (1 << 17) /* Runt Frame */
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#define RDES_CE (1 << 16) /* CRC error */
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#define RDES_FT (1 << 15) /* Frame Type */
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#define RDES_FLEN (0x7ff) /* Frame Length */
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#define RDES_RER (1 << 25) /* Receive End of Ring */
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#define RDES_RBS (0x7ff) /* Receive Buffer Size */
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/* Transmit descriptor flags */
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#define TDES_OWN (1 << 31) /* Ownership */
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#define TDES_IC (1 << 31) /* Interrupt on Completion */
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#define TDES_FS (1 << 30) /* First Segment */
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#define TDES_LS (1 << 29) /* Last Segment */
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#define TDES_IPCKG (1 << 28) /* IP Checksum generate */
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#define TDES_TCPCKG (1 << 27) /* TCP Checksum generate */
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#define TDES_UDPCKG (1 << 26) /* UDP Checksum generate */
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#define TDES_TER (1 << 25) /* Transmit End of Ring */
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#define TDES_TBS (0x7ff) /* Transmit Buffer Size */
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/*
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* Network controller register offsets
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*/
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#define KS8695_DTXC (0x00) /* DMA Transmit Control */
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#define KS8695_DRXC (0x04) /* DMA Receive Control */
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#define KS8695_DTSC (0x08) /* DMA Transmit Start Command */
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#define KS8695_DRSC (0x0c) /* DMA Receive Start Command */
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#define KS8695_TDLB (0x10) /* Transmit Descriptor List
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* Base Address
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*/
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#define KS8695_RDLB (0x14) /* Receive Descriptor List
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* Base Address
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*/
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#define KS8695_MAL (0x18) /* MAC Station Address Low */
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#define KS8695_MAH (0x1c) /* MAC Station Address High */
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#define KS8695_AAL_(n) (0x80 + ((n)*8)) /* MAC Additional
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* Station Address
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* (0..15) Low
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*/
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#define KS8695_AAH_(n) (0x84 + ((n)*8)) /* MAC Additional
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* Station Address
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* (0..15) High
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*/
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/* DMA Transmit Control Register */
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#define DTXC_TRST (1 << 31) /* Soft Reset */
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#define DTXC_TBS (0x3f << 24) /* Transmit Burst Size */
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#define DTXC_TUCG (1 << 18) /* Transmit UDP
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* Checksum Generate
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*/
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#define DTXC_TTCG (1 << 17) /* Transmit TCP
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* Checksum Generate
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*/
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#define DTXC_TICG (1 << 16) /* Transmit IP
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* Checksum Generate
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*/
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#define DTXC_TFCE (1 << 9) /* Transmit Flow
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* Control Enable
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*/
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#define DTXC_TLB (1 << 8) /* Loopback mode */
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#define DTXC_TEP (1 << 2) /* Transmit Enable Padding */
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#define DTXC_TAC (1 << 1) /* Transmit Add CRC */
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#define DTXC_TE (1 << 0) /* TX Enable */
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/* DMA Receive Control Register */
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#define DRXC_RBS (0x3f << 24) /* Receive Burst Size */
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#define DRXC_RUCC (1 << 18) /* Receive UDP Checksum check */
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#define DRXC_RTCG (1 << 17) /* Receive TCP Checksum check */
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#define DRXC_RICG (1 << 16) /* Receive IP Checksum check */
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#define DRXC_RFCE (1 << 9) /* Receive Flow Control
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* Enable
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*/
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#define DRXC_RB (1 << 6) /* Receive Broadcast */
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#define DRXC_RM (1 << 5) /* Receive Multicast */
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#define DRXC_RU (1 << 4) /* Receive Unicast */
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#define DRXC_RERR (1 << 3) /* Receive Error Frame */
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#define DRXC_RA (1 << 2) /* Receive All */
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#define DRXC_RE (1 << 0) /* RX Enable */
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/* Additional Station Address High */
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#define AAH_E (1 << 31) /* Address Enabled */
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#endif /* KS8695NET_H */
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