/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, Intel Corporation. */
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#ifndef _ICE_TYPE_H_
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#define _ICE_TYPE_H_
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#include "ice_status.h"
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#include "ice_hw_autogen.h"
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#include "ice_osdep.h"
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#include "ice_controlq.h"
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#include "ice_lan_tx_rx.h"
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#define ICE_BYTES_PER_WORD 2
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#define ICE_BYTES_PER_DWORD 4
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static inline bool ice_is_tc_ena(u8 bitmap, u8 tc)
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{
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return test_bit(tc, (unsigned long *)&bitmap);
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}
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/* debug masks - set these bits in hw->debug_mask to control output */
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#define ICE_DBG_INIT BIT_ULL(1)
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#define ICE_DBG_LINK BIT_ULL(4)
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#define ICE_DBG_QCTX BIT_ULL(6)
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#define ICE_DBG_NVM BIT_ULL(7)
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#define ICE_DBG_LAN BIT_ULL(8)
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#define ICE_DBG_SW BIT_ULL(13)
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#define ICE_DBG_SCHED BIT_ULL(14)
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#define ICE_DBG_RES BIT_ULL(17)
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#define ICE_DBG_AQ_MSG BIT_ULL(24)
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#define ICE_DBG_AQ_CMD BIT_ULL(27)
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#define ICE_DBG_USER BIT_ULL(31)
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enum ice_aq_res_ids {
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ICE_NVM_RES_ID = 1,
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ICE_SPD_RES_ID,
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ICE_CHANGE_LOCK_RES_ID,
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ICE_GLOBAL_CFG_LOCK_RES_ID
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};
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/* FW update timeout definitions are in milliseconds */
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#define ICE_NVM_TIMEOUT 180000
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#define ICE_CHANGE_LOCK_TIMEOUT 1000
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#define ICE_GLOBAL_CFG_LOCK_TIMEOUT 5000
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enum ice_aq_res_access_type {
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ICE_RES_READ = 1,
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ICE_RES_WRITE
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};
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enum ice_fc_mode {
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ICE_FC_NONE = 0,
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ICE_FC_RX_PAUSE,
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ICE_FC_TX_PAUSE,
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ICE_FC_FULL,
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ICE_FC_PFC,
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ICE_FC_DFLT
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};
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enum ice_set_fc_aq_failures {
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ICE_SET_FC_AQ_FAIL_NONE = 0,
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ICE_SET_FC_AQ_FAIL_GET,
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ICE_SET_FC_AQ_FAIL_SET,
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ICE_SET_FC_AQ_FAIL_UPDATE
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};
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/* Various MAC types */
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enum ice_mac_type {
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ICE_MAC_UNKNOWN = 0,
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ICE_MAC_GENERIC,
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};
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/* Media Types */
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enum ice_media_type {
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ICE_MEDIA_UNKNOWN = 0,
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ICE_MEDIA_FIBER,
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ICE_MEDIA_BASET,
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ICE_MEDIA_BACKPLANE,
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ICE_MEDIA_DA,
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};
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enum ice_vsi_type {
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ICE_VSI_PF = 0,
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};
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struct ice_link_status {
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/* Refer to ice_aq_phy_type for bits definition */
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u64 phy_type_low;
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u16 max_frame_size;
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u16 link_speed;
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u16 req_speeds;
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u8 lse_ena; /* Link Status Event notification */
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u8 link_info;
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u8 an_info;
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u8 ext_info;
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u8 pacing;
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/* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
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* ice_aqc_get_phy_caps structure
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*/
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u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
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};
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/* PHY info such as phy_type, etc... */
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struct ice_phy_info {
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struct ice_link_status link_info;
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struct ice_link_status link_info_old;
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u64 phy_type_low;
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enum ice_media_type media_type;
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u8 get_link_info;
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};
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/* Common HW capabilities for SW use */
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struct ice_hw_common_caps {
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/* TX/RX queues */
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u16 num_rxq; /* Number/Total RX queues */
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u16 rxq_first_id; /* First queue ID for RX queues */
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u16 num_txq; /* Number/Total TX queues */
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u16 txq_first_id; /* First queue ID for TX queues */
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/* MSI-X vectors */
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u16 num_msix_vectors;
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u16 msix_vector_first_id;
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/* Max MTU for function or device */
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u16 max_mtu;
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/* RSS related capabilities */
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u16 rss_table_size; /* 512 for PFs and 64 for VFs */
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u8 rss_table_entry_width; /* RSS Entry width in bits */
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};
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/* Function specific capabilities */
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struct ice_hw_func_caps {
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struct ice_hw_common_caps common_cap;
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u32 guaranteed_num_vsi;
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};
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/* Device wide capabilities */
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struct ice_hw_dev_caps {
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struct ice_hw_common_caps common_cap;
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u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
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};
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/* MAC info */
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struct ice_mac_info {
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u8 lan_addr[ETH_ALEN];
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u8 perm_addr[ETH_ALEN];
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};
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/* Various RESET request, These are not tied with HW reset types */
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enum ice_reset_req {
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ICE_RESET_PFR = 0,
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ICE_RESET_CORER = 1,
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ICE_RESET_GLOBR = 2,
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};
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/* Bus parameters */
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struct ice_bus_info {
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u16 device;
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u8 func;
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};
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/* Flow control (FC) parameters */
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struct ice_fc_info {
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enum ice_fc_mode current_mode; /* FC mode in effect */
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enum ice_fc_mode req_mode; /* FC mode requested by caller */
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};
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/* NVM Information */
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struct ice_nvm_info {
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u32 eetrack; /* NVM data version */
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u32 oem_ver; /* OEM version info */
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u16 sr_words; /* Shadow RAM size in words */
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u16 ver; /* NVM package version */
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u8 blank_nvm_mode; /* is NVM empty (no FW present) */
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};
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/* Max number of port to queue branches w.r.t topology */
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#define ICE_MAX_TRAFFIC_CLASS 8
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#define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
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struct ice_sched_node {
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struct ice_sched_node *parent;
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struct ice_sched_node *sibling; /* next sibling in the same layer */
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struct ice_sched_node **children;
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struct ice_aqc_txsched_elem_data info;
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u32 agg_id; /* aggregator group id */
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u16 vsi_id;
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u8 in_use; /* suspended or in use */
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u8 tx_sched_layer; /* Logical Layer (1-9) */
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u8 num_children;
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u8 tc_num;
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u8 owner;
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#define ICE_SCHED_NODE_OWNER_LAN 0
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};
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/* Access Macros for Tx Sched Elements data */
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#define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
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/* The aggregator type determines if identifier is for a VSI group,
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* aggregator group, aggregator of queues, or queue group.
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*/
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enum ice_agg_type {
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ICE_AGG_TYPE_UNKNOWN = 0,
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ICE_AGG_TYPE_VSI,
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ICE_AGG_TYPE_AGG, /* aggregator */
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ICE_AGG_TYPE_Q,
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ICE_AGG_TYPE_QG
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};
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#define ICE_SCHED_DFLT_RL_PROF_ID 0
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/* vsi type list entry to locate corresponding vsi/ag nodes */
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struct ice_sched_vsi_info {
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struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
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struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
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struct list_head list_entry;
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u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
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u16 vsi_id;
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};
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/* driver defines the policy */
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struct ice_sched_tx_policy {
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u16 max_num_vsis;
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u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
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u8 rdma_ena;
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};
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struct ice_port_info {
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struct ice_sched_node *root; /* Root Node per Port */
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struct ice_hw *hw; /* back pointer to hw instance */
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u32 last_node_teid; /* scheduler last node info */
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u16 sw_id; /* Initial switch ID belongs to port */
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u16 pf_vf_num;
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u8 port_state;
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#define ICE_SCHED_PORT_STATE_INIT 0x0
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#define ICE_SCHED_PORT_STATE_READY 0x1
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u16 dflt_tx_vsi_rule_id;
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u16 dflt_tx_vsi_num;
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u16 dflt_rx_vsi_rule_id;
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u16 dflt_rx_vsi_num;
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struct ice_fc_info fc;
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struct ice_mac_info mac;
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struct ice_phy_info phy;
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struct mutex sched_lock; /* protect access to TXSched tree */
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struct ice_sched_tx_policy sched_policy;
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struct list_head vsi_info_list;
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struct list_head agg_list; /* lists all aggregator */
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u8 lport;
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#define ICE_LPORT_MASK 0xff
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u8 is_vf;
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};
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struct ice_switch_info {
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/* Switch VSI lists to MAC/VLAN translation */
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struct mutex mac_list_lock; /* protect MAC list */
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struct list_head mac_list_head;
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struct mutex vlan_list_lock; /* protect VLAN list */
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struct list_head vlan_list_head;
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struct mutex eth_m_list_lock; /* protect ethtype list */
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struct list_head eth_m_list_head;
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struct mutex promisc_list_lock; /* protect promisc mode list */
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struct list_head promisc_list_head;
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struct mutex mac_vlan_list_lock; /* protect MAC-VLAN list */
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struct list_head mac_vlan_list_head;
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struct list_head vsi_list_map_head;
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};
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/* Port hardware description */
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struct ice_hw {
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u8 __iomem *hw_addr;
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void *back;
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struct ice_aqc_layer_props *layer_info;
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struct ice_port_info *port_info;
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u64 debug_mask; /* bitmap for debug mask */
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enum ice_mac_type mac_type;
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/* pci info */
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u16 device_id;
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u16 vendor_id;
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u16 subsystem_device_id;
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u16 subsystem_vendor_id;
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u8 revision_id;
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u8 pf_id; /* device profile info */
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/* TX Scheduler values */
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u16 num_tx_sched_layers;
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u16 num_tx_sched_phys_layers;
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u8 flattened_layers;
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u8 max_cgds;
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u8 sw_entry_point_layer;
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u8 evb_veb; /* true for VEB, false for VEPA */
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u8 reset_ongoing; /* true if hw is in reset, false otherwise */
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struct ice_bus_info bus;
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struct ice_nvm_info nvm;
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struct ice_hw_dev_caps dev_caps; /* device capabilities */
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struct ice_hw_func_caps func_caps; /* function capabilities */
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struct ice_switch_info *switch_info; /* switch filter lists */
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/* Control Queue info */
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struct ice_ctl_q_info adminq;
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u8 api_branch; /* API branch version */
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u8 api_maj_ver; /* API major version */
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u8 api_min_ver; /* API minor version */
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u8 api_patch; /* API patch version */
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u8 fw_branch; /* firmware branch version */
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u8 fw_maj_ver; /* firmware major version */
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u8 fw_min_ver; /* firmware minor version */
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u8 fw_patch; /* firmware patch version */
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u32 fw_build; /* firmware build number */
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/* minimum allowed value for different speeds */
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#define ICE_ITR_GRAN_MIN_200 1
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#define ICE_ITR_GRAN_MIN_100 1
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#define ICE_ITR_GRAN_MIN_50 2
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#define ICE_ITR_GRAN_MIN_25 4
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/* ITR granularity in 1 us */
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u8 itr_gran_200;
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u8 itr_gran_100;
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u8 itr_gran_50;
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u8 itr_gran_25;
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u8 ucast_shared; /* true if VSIs can share unicast addr */
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};
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/* Statistics collected by each port, VSI, VEB, and S-channel */
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struct ice_eth_stats {
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u64 rx_bytes; /* gorc */
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u64 rx_unicast; /* uprc */
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u64 rx_multicast; /* mprc */
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u64 rx_broadcast; /* bprc */
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u64 rx_discards; /* rdpc */
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u64 rx_unknown_protocol; /* rupp */
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u64 tx_bytes; /* gotc */
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u64 tx_unicast; /* uptc */
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u64 tx_multicast; /* mptc */
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u64 tx_broadcast; /* bptc */
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u64 tx_discards; /* tdpc */
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u64 tx_errors; /* tepc */
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};
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/* Statistics collected by the MAC */
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struct ice_hw_port_stats {
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/* eth stats collected by the port */
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struct ice_eth_stats eth;
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/* additional port specific stats */
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u64 tx_dropped_link_down; /* tdold */
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u64 crc_errors; /* crcerrs */
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u64 illegal_bytes; /* illerrc */
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u64 error_bytes; /* errbc */
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u64 mac_local_faults; /* mlfc */
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u64 mac_remote_faults; /* mrfc */
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u64 rx_len_errors; /* rlec */
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u64 link_xon_rx; /* lxonrxc */
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u64 link_xoff_rx; /* lxoffrxc */
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u64 link_xon_tx; /* lxontxc */
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u64 link_xoff_tx; /* lxofftxc */
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u64 rx_size_64; /* prc64 */
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u64 rx_size_127; /* prc127 */
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u64 rx_size_255; /* prc255 */
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u64 rx_size_511; /* prc511 */
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u64 rx_size_1023; /* prc1023 */
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u64 rx_size_1522; /* prc1522 */
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u64 rx_size_big; /* prc9522 */
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u64 rx_undersize; /* ruc */
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u64 rx_fragments; /* rfc */
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u64 rx_oversize; /* roc */
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u64 rx_jabber; /* rjc */
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u64 tx_size_64; /* ptc64 */
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u64 tx_size_127; /* ptc127 */
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u64 tx_size_255; /* ptc255 */
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u64 tx_size_511; /* ptc511 */
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u64 tx_size_1023; /* ptc1023 */
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u64 tx_size_1522; /* ptc1522 */
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u64 tx_size_big; /* ptc9522 */
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};
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/* Checksum and Shadow RAM pointers */
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#define ICE_SR_NVM_DEV_STARTER_VER 0x18
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#define ICE_SR_NVM_EETRACK_LO 0x2D
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#define ICE_SR_NVM_EETRACK_HI 0x2E
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#define ICE_NVM_VER_LO_SHIFT 0
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#define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
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#define ICE_NVM_VER_HI_SHIFT 12
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#define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
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#define ICE_OEM_VER_PATCH_SHIFT 0
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#define ICE_OEM_VER_PATCH_MASK (0xff << ICE_OEM_VER_PATCH_SHIFT)
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#define ICE_OEM_VER_BUILD_SHIFT 8
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#define ICE_OEM_VER_BUILD_MASK (0xffff << ICE_OEM_VER_BUILD_SHIFT)
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#define ICE_OEM_VER_SHIFT 24
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#define ICE_OEM_VER_MASK (0xff << ICE_OEM_VER_SHIFT)
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#define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
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#define ICE_SR_WORDS_IN_1KB 512
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#endif /* _ICE_TYPE_H_ */
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