/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*/
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#ifndef ROCKCHIP_MIPI_CSI_TX
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#define ROCKCHIP_MIPI_CSI_TX
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#define DRIVER_NAME "rockchip-mipi-csi"
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#define CSITX_CONFIG_DONE 0x0000
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#define m_CONFIG_DONE BIT(0)
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#define m_CONFIG_DONE_IMD BIT(4)
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#define m_CONFIG_DONE_MODE BIT(8)
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#define v_CONFIG_DONE(x) (((x) & 0x1) << 0)
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#define v_CONFIG_DONE_IMD(x) (((x) & 0x1) << 4)
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#define v_CONFIG_DONE_MODE(x) (((x) & 0x1) << 8)
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enum CONFIG_DONE_MODE {
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FRAME_END_RX_MODE,
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FRAME_END_TX_MODE
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};
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#define CSITX_ENABLE 0x0004
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#define m_CSITX_EN BIT(0)
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#define m_CPHY_EN BIT(1)
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#define m_DPHY_EN BIT(2)
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#define m_LANE_NUM GENMASK(5, 4)
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#define m_IDI_48BIT_EN BIT(9)
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#define v_CSITX_EN(x) (((x) & 0x1) << 0)
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#define v_CPHY_EN(x) (((x) & 0x1) << 1)
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#define v_DPHY_EN(x) (((x) & 0x1) << 2)
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#define v_LANE_NUM(x) (((x) & 0x3) << 4)
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#define v_IDI_48BIT_EN(x) (((x) & 0x1) << 9)
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#define CSITX_VERSION 0x0008
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#define CSITX_SYS_CTRL0 0x0010
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#define m_SOFT_RESET BIT(0)
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#define v_SOFT_RESET(x) (((x) & 0x1) << 0)
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#define CSITX_SYS_CTRL1 0x0014
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#define m_BYPASS_SELECT BIT(0)
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#define v_BYPASS_SELECT(x) (((x) & 0x1) << 0)
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#define CSITX_SYS_CTRL2 0x0018
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#define m_VSYNC_ENABLE BIT(0)
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#define m_HSYNC_ENABLE BIT(1)
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#define m_IDI_WHOLE_FRM_EN BIT(4)
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#define m_VOP_WHOLE_FRM_EN BIT(5)
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#define v_VSYNC_ENABLE(x) (((x) & 0x1) << 0)
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#define v_HSYNC_ENABLE(x) (((x) & 0x1) << 1)
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#define v_IDI_WHOLE_FRM_EN(x) (((x) & 0x1) << 4)
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#define v_VOP_WHOLE_FRM_EN(x) (((x) & 0x1) << 5)
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#define CSITX_SYS_CTRL3 0x001c
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#define m_NON_CONTINUES_MODE_EN BIT(0)
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#define m_CONT_MODE_CLK_SET BIT(4)
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#define m_CONT_MODE_CLK_CLR BIT(8)
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#define v_NON_CONTINUES_MODE_EN(x) (((x) & 0x1) << 0)
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#define v_CONT_MODE_CLK_SET(x) (((x) & 0x1) << 4)
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#define v_CONT_MODE_CLK_CLR(x) (((x) & 0x1) << 8)
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#define CSITX_TIMING_CTRL 0x0020
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#define CSITX_TIMING_VPW_NUM 0x0024
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#define CSITX_TIMING_VBP_NUM 0x0028
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#define CSITX_TIMING_VFP_NUM 0x002c
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#define CSITX_TIMING_HPW_PADDING_NUM 0x0030
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#define CSITX_VOP_PATH_CTRL 0x0040
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#define m_VOP_PATH_EN BIT(0)
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#define m_VOP_DT_USERDEFINE_EN BIT(1)
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#define m_VOP_VC_USERDEFINE_EN BIT(2)
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#define m_VOP_WC_USERDEFINE_EN BIT(3)
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#define m_PIXEL_FORMAT GENMASK(7, 4)
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#define m_VOP_DT_USERDEFINE GENMASK(13, 8)
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#define m_VOP_VC_USERDEFINE GENMASK(15, 14)
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#define m_VOP_WC_USERDEFINE GENMASK(31, 16)
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#define v_VOP_PATH_EN(x) (((x) & 0x1) << 0)
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#define v_VOP_DT_USERDEFINE_EN(x) (((x) & 0x1) << 1)
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#define v_VOP_VC_USERDEFINE_EN(x) (((x) & 0x1) << 2)
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#define v_VOP_WC_USERDEFINE_EN(x) (((x) & 0x1) << 3)
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#define v_PIXEL_FORMAT(x) (((x) & 0xf) << 4)
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#define v_VOP_DT_USERDEFINE(x) (((x) & 0x3f) << 8)
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#define v_VOP_VC_USERDEFINE(x) (((x) & 0x3) << 14)
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#define v_VOP_WC_USERDEFINE(x) (((x) & 0xffff) << 16)
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#define CSITX_VOP_PATH_PKT_CTRL 0x0050
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#define m_VOP_LINE_PADDING_EN BIT(4)
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#define m_VOP_LINE_PADDING_NUM GENMASK(7, 5)
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#define m_VOP_PKT_PADDING_EN BIT(8)
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#define m_VOP_WC_ACTIVE GENMASK(31, 16)
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#define v_VOP_LINE_PADDING_EN(x) (((x) & 0x1) << 4)
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#define v_VOP_LINE_PADDING_NUM(x) (((x) & 0x7) << 5)
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#define v_VOP_PKT_PADDING_EN(x) (((x) & 0x1) << 8)
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#define v_VOP_WC_ACTIVE(x) (((x) & 0xff) << 16)
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#define CSITX_BYPASS_PATH_CTRL 0x0060
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#define m_BYPASS_PATH_EN BIT(0)
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#define m_BYPASS_DT_USERDEFINE_EN BIT(1)
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#define m_BYPASS_VC_USERDEFINE_EN BIT(2)
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#define m_BYPASS_WC_USERDEFINE_EN BIT(3)
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#define m_CAM_FORMAT GENMASK(7, 4)
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#define m_BYPASS_DT_USERDEFINE GENMASK(13, 8)
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#define m_BYPASS_VC_USERDEFINE GENMASK(15, 14)
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#define m_BYPASS_WC_USERDEFINE GENMASK(31, 16)
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#define v_BYPASS_PATH_EN(x) (((x) & 0x1) << 0)
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#define v_BYPASS_DT_USERDEFINE_EN(x) (((x) & 0x1) << 1)
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#define v_BYPASS_VC_USERDEFINE_EN(x) (((x) & 0x1) << 2)
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#define v_BYPASS_WC_USERDEFINE_EN(x) (((x) & 0x1) << 3)
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#define v_CAM_FORMAT(x) (((x) & 0xf) << 4)
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#define v_BYPASS_DT_USERDEFINE(x) (((x) & 0x3f) << 8)
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#define v_BYPASS_VC_USERDEFINE(x) (((x) & 0x3) << 14)
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#define v_BYPASS_WC_USERDEFINE(x) (((x) & 0xff) << 16)
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#define CSITX_BYPASS_PATH_PKT_CTRL 0x0064
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#define m_BYPASS_LINE_PADDING_EN BIT(4)
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#define m_BYPASS_LINE_PADDING_NUM GENMASK(7, 5)
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#define m_BYPASS_PKT_PADDING_EN BIT(8)
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#define m_BYPASS_WC_ACTIVE GENMASK(31, 16)
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#define v_BYPASS_LINE_PADDING_EN(x) (((x) & 0x1) << 4)
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#define v_BYPASS_LINE_PADDING_NUM(x) (((x) & 0x7) << 5)
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#define v_BYPASS_PKT_PADDING_EN(x) (((x) & 0x1) << 8)
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#define v_BYPASS_WC_ACTIVE(x) (((x) & 0xff) << 16)
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#define CSITX_STATUS0 0x0070
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#define CSITX_STATUS1 0x0074
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#define m_DPHY_PLL_LOCK BIT(0)
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#define m_STOPSTATE_CLK BIT(1)
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#define m_STOPSTATE_LANE GENMASK(7, 4)
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#define PHY_STOPSTATELANE (m_STOPSTATE_CLK | m_STOPSTATE_LANE)
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#define CSITX_STATUS2 0x0078
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#define CSITX_LINE_FLAG_NUM 0x007c
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#define CSITX_INTR_EN 0x0080
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#define m_INTR_MASK GENMASK(26, 16)
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#define m_FRM_ST_RX BIT(0 + 16)
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#define m_FRM_END_RX BIT(1 + 16)
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#define m_LINE_END_TX BIT(2 + 16)
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#define m_FRM_ST_TX BIT(3 + 16)
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#define m_FRM_END_TX BIT(4 + 16)
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#define m_LINE_END_RX BIT(5 + 16)
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#define m_LINE_FLAG0 BIT(6 + 16)
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#define m_LINE_FLAG1 BIT(7 + 16)
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#define m_STOP_STATE BIT(8 + 16)
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#define m_PLL_LOCK BIT(9 + 16)
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#define m_CSITX_IDLE BIT(10 + 16)
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#define v_FRM_ST_RX(x) (((x) & 0x1) << 0)
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#define v_FRM_END_RX(x) (((x) & 0x1) << 1)
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#define v_LINE_END_TX(x) (((x) & 0x1) << 2)
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#define v_FRM_ST_TX(x) (((x) & 0x1) << 3)
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#define v_FRM_END_TX(x) (((x) & 0x1) << 4)
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#define v_LINE_END_RX(x) (((x) & 0x1) << 5)
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#define v_LINE_FLAG0(x) (((x) & 0x1) << 6)
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#define v_LINE_FLAG1(x) (((x) & 0x1) << 7)
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#define v_STOP_STATE(x) (((x) & 0x1) << 8)
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#define v_PLL_LOCK(x) (((x) & 0x1) << 9)
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#define v_CSITX_IDLE(x) (((x) & 0x1) << 10)
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#define CSITX_INTR_CLR 0x0084
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#define CSITX_INTR_STATUS 0x0088
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#define CSITX_INTR_RAW_STATUS 0x008c
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#define CSITX_ERR_INTR_EN 0x0090
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#define m_ERR_INTR_EN GENMASK(11, 0)
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#define m_ERR_INTR_MASK GENMASK(27, 16)
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#define m_IDI_HDR_FIFO_OVERFLOW BIT(0 + 16)
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#define m_IDI_HDR_FIFO_UNDERFLOW BIT(1 + 16)
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#define m_IDI_PLD_FIFO_OVERFLOW BIT(2 + 16)
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#define m_IDI_PLD_FIFO_UNDERFLOW BIT(3 + 16)
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#define m_HDR_FIFO_OVERFLOW BIT(4 + 16)
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#define m_HDR_FIFO_UNDERFLOW BIT(5 + 16)
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#define m_PLD_FIFO_OVERFLOW BIT(6 + 16)
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#define m_PLD_FIFO_UNDERFLOW BIT(7 + 16)
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#define m_OUTBUFFER_OVERFLOW BIT(8 + 16)
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#define m_OUTBUFFER_UNDERFLOW BIT(9 + 16)
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#define m_TX_TXREADYHS_OVERFLOW BIT(10 + 16)
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#define m_TX_TXREADYHS_UNDERFLOW BIT(11 + 16)
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#define CSITX_ERR_INTR_CLR 0x0094
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#define CSITX_ERR_INTR_STATUS 0x0098
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#define CSITX_ERR_INTR_RAW_STATUS 0x009c
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#define CSITX_ULPS_CTRL 0x00a0
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#define CSITX_LPDT_CTRL 0x00a4
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#define CSITX_LPDT_DATA 0x00a8
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#define CSITX_DPHY_CTRL 0x00b0
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#define m_CSITX_ENABLE_PHY GENMASK(7, 3)
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#define v_CSITX_ENABLE_PHY(x) (((x) & 0x1f) << 3)
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#define CSITX_DPHY_PPI_CTRL 0x00b4
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#define CSITX_DPHY_TEST_CTRL 0x00b8
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#define CSITX_DPHY_ERROR 0x00bc
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#define CSITX_DPHY_SCAN_CTRL 0x00c0
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#define CSITX_DPHY_SCANIN 0x00c4
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#define CSITX_DPHY_SCANOUT 0x00c8
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#define CSITX_DPHY_BIST 0x00d0
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#define MIPI_CSI_FMT_RAW8 0x10
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#define MIPI_CSI_FMT_RAW10 0x11
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#define PHY_STATUS_TIMEOUT_US 10000
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#define CMD_PKT_STATUS_TIMEOUT_US 20000
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#define RK_CSI_TX_MAX_RESET 5
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enum soc_type {
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RK1808,
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};
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enum csi_path_mode {
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VOP_PATH,
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BYPASS_PATH
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};
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#define GRF_REG_FIELD(reg, lsb, msb) ((reg << 16) | (lsb << 8) | (msb))
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enum grf_reg_fields {
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DPIUPDATECFG,
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DPISHUTDN,
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DPICOLORM,
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VOPSEL,
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TURNREQUEST,
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TURNDISABLE,
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FORCETXSTOPMODE,
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FORCERXMODE,
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ENABLE_N,
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MASTERSLAVEZ,
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ENABLECLK,
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BASEDIR,
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DPHY_SEL,
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TXSKEWCALHS,
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MAX_FIELDS,
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};
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struct rockchip_mipi_csi_plat_data {
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const u32 *csi0_grf_reg_fields;
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const u32 *csi1_grf_reg_fields;
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unsigned long max_bit_rate_per_lane;
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enum soc_type soc_type;
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const char * const *rsts;
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int rsts_num;
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};
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struct mipi_dphy {
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/* SNPS PHY */
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struct clk *cfg_clk;
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struct clk *ref_clk;
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u16 input_div;
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u16 feedback_div;
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/* Non-SNPS PHY */
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struct phy *phy;
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struct clk *hs_clk;
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};
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struct rockchip_mipi_csi {
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struct drm_encoder encoder;
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struct drm_connector connector;
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struct device_node *client;
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struct mipi_dsi_host dsi_host;
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struct mipi_dphy dphy;
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struct drm_panel *panel;
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struct device *dev;
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struct regmap *grf;
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struct reset_control *tx_rsts[RK_CSI_TX_MAX_RESET];
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void __iomem *regs;
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void __iomem *test_code_regs;
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struct regmap *regmap;
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u32 *regsbak;
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u32 regs_len;
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struct clk *pclk;
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struct clk *ref_clk;
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int irq;
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unsigned long mode_flags;
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unsigned int lane_mbps; /* per lane */
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u32 channel;
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u32 lanes;
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u32 format;
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struct drm_display_mode mode;
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u32 path_mode; /* vop path or bypass path */
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struct drm_property *csi_tx_path_property;
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const struct rockchip_mipi_csi_plat_data *pdata;
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};
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enum rockchip_mipi_csi_mode {
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DSI_COMMAND_MODE,
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DSI_VIDEO_MODE,
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};
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#endif
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