/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DPU_HW_INTERRUPTS_H
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#define _DPU_HW_INTERRUPTS_H
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#include <linux/types.h>
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#include "dpu_hwio.h"
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#include "dpu_hw_catalog.h"
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#include "dpu_hw_util.h"
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#include "dpu_hw_mdss.h"
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#define IRQ_SOURCE_MDP BIT(0)
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#define IRQ_SOURCE_DSI0 BIT(4)
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#define IRQ_SOURCE_DSI1 BIT(5)
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#define IRQ_SOURCE_HDMI BIT(8)
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#define IRQ_SOURCE_EDP BIT(12)
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#define IRQ_SOURCE_MHL BIT(16)
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/**
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* dpu_intr_type - HW Interrupt Type
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* @DPU_IRQ_TYPE_WB_ROT_COMP: WB rotator done
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* @DPU_IRQ_TYPE_WB_WFD_COMP: WB WFD done
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* @DPU_IRQ_TYPE_PING_PONG_COMP: PingPong done
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* @DPU_IRQ_TYPE_PING_PONG_RD_PTR: PingPong read pointer
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* @DPU_IRQ_TYPE_PING_PONG_WR_PTR: PingPong write pointer
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* @DPU_IRQ_TYPE_PING_PONG_AUTO_REF: PingPong auto refresh
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* @DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK: PingPong Tear check
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* @DPU_IRQ_TYPE_PING_PONG_TE_CHECK: PingPong TE detection
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* @DPU_IRQ_TYPE_INTF_UNDER_RUN: INTF underrun
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* @DPU_IRQ_TYPE_INTF_VSYNC: INTF VSYNC
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* @DPU_IRQ_TYPE_CWB_OVERFLOW: Concurrent WB overflow
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* @DPU_IRQ_TYPE_HIST_VIG_DONE: VIG Histogram done
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* @DPU_IRQ_TYPE_HIST_VIG_RSTSEQ: VIG Histogram reset
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* @DPU_IRQ_TYPE_HIST_DSPP_DONE: DSPP Histogram done
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* @DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ: DSPP Histogram reset
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* @DPU_IRQ_TYPE_WD_TIMER: Watchdog timer
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* @DPU_IRQ_TYPE_SFI_VIDEO_IN: Video static frame INTR into static
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* @DPU_IRQ_TYPE_SFI_VIDEO_OUT: Video static frame INTR out-of static
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* @DPU_IRQ_TYPE_SFI_CMD_0_IN: DSI CMD0 static frame INTR into static
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* @DPU_IRQ_TYPE_SFI_CMD_0_OUT: DSI CMD0 static frame INTR out-of static
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* @DPU_IRQ_TYPE_SFI_CMD_1_IN: DSI CMD1 static frame INTR into static
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* @DPU_IRQ_TYPE_SFI_CMD_1_OUT: DSI CMD1 static frame INTR out-of static
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* @DPU_IRQ_TYPE_SFI_CMD_2_IN: DSI CMD2 static frame INTR into static
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* @DPU_IRQ_TYPE_SFI_CMD_2_OUT: DSI CMD2 static frame INTR out-of static
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* @DPU_IRQ_TYPE_PROG_LINE: Programmable Line interrupt
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* @DPU_IRQ_TYPE_AD4_BL_DONE: AD4 backlight
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* @DPU_IRQ_TYPE_CTL_START: Control start
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* @DPU_IRQ_TYPE_RESERVED: Reserved for expansion
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*/
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enum dpu_intr_type {
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DPU_IRQ_TYPE_WB_ROT_COMP,
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DPU_IRQ_TYPE_WB_WFD_COMP,
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DPU_IRQ_TYPE_PING_PONG_COMP,
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DPU_IRQ_TYPE_PING_PONG_RD_PTR,
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DPU_IRQ_TYPE_PING_PONG_WR_PTR,
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DPU_IRQ_TYPE_PING_PONG_AUTO_REF,
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DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK,
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DPU_IRQ_TYPE_PING_PONG_TE_CHECK,
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DPU_IRQ_TYPE_INTF_UNDER_RUN,
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DPU_IRQ_TYPE_INTF_VSYNC,
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DPU_IRQ_TYPE_CWB_OVERFLOW,
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DPU_IRQ_TYPE_HIST_VIG_DONE,
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DPU_IRQ_TYPE_HIST_VIG_RSTSEQ,
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DPU_IRQ_TYPE_HIST_DSPP_DONE,
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DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ,
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DPU_IRQ_TYPE_WD_TIMER,
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DPU_IRQ_TYPE_SFI_VIDEO_IN,
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DPU_IRQ_TYPE_SFI_VIDEO_OUT,
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DPU_IRQ_TYPE_SFI_CMD_0_IN,
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DPU_IRQ_TYPE_SFI_CMD_0_OUT,
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DPU_IRQ_TYPE_SFI_CMD_1_IN,
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DPU_IRQ_TYPE_SFI_CMD_1_OUT,
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DPU_IRQ_TYPE_SFI_CMD_2_IN,
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DPU_IRQ_TYPE_SFI_CMD_2_OUT,
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DPU_IRQ_TYPE_PROG_LINE,
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DPU_IRQ_TYPE_AD4_BL_DONE,
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DPU_IRQ_TYPE_CTL_START,
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DPU_IRQ_TYPE_RESERVED,
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};
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struct dpu_hw_intr;
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/**
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* Interrupt operations.
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*/
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struct dpu_hw_intr_ops {
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/**
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* set_mask - Programs the given interrupt register with the
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* given interrupt mask. Register value will get overwritten.
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* @intr: HW interrupt handle
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* @reg_off: MDSS HW register offset
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* @irqmask: IRQ mask value
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*/
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void (*set_mask)(
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struct dpu_hw_intr *intr,
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uint32_t reg,
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uint32_t irqmask);
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/**
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* irq_idx_lookup - Lookup IRQ index on the HW interrupt type
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* Used for all irq related ops
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* @intr_type: Interrupt type defined in dpu_intr_type
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* @instance_idx: HW interrupt block instance
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* @return: irq_idx or -EINVAL for lookup fail
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*/
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int (*irq_idx_lookup)(
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enum dpu_intr_type intr_type,
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u32 instance_idx);
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/**
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* enable_irq - Enable IRQ based on lookup IRQ index
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* @intr: HW interrupt handle
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* @irq_idx: Lookup irq index return from irq_idx_lookup
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* @return: 0 for success, otherwise failure
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*/
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int (*enable_irq)(
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struct dpu_hw_intr *intr,
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int irq_idx);
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/**
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* disable_irq - Disable IRQ based on lookup IRQ index
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* @intr: HW interrupt handle
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* @irq_idx: Lookup irq index return from irq_idx_lookup
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* @return: 0 for success, otherwise failure
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*/
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int (*disable_irq)(
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struct dpu_hw_intr *intr,
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int irq_idx);
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/**
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* clear_all_irqs - Clears all the interrupts (i.e. acknowledges
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* any asserted IRQs). Useful during reset.
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* @intr: HW interrupt handle
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* @return: 0 for success, otherwise failure
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*/
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int (*clear_all_irqs)(
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struct dpu_hw_intr *intr);
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/**
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* disable_all_irqs - Disables all the interrupts. Useful during reset.
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* @intr: HW interrupt handle
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* @return: 0 for success, otherwise failure
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*/
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int (*disable_all_irqs)(
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struct dpu_hw_intr *intr);
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/**
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* dispatch_irqs - IRQ dispatcher will call the given callback
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* function when a matching interrupt status bit is
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* found in the irq mapping table.
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* @intr: HW interrupt handle
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* @cbfunc: Callback function pointer
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* @arg: Argument to pass back during callback
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*/
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void (*dispatch_irqs)(
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struct dpu_hw_intr *intr,
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void (*cbfunc)(void *arg, int irq_idx),
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void *arg);
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/**
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* get_interrupt_statuses - Gets and store value from all interrupt
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* status registers that are currently fired.
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* @intr: HW interrupt handle
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*/
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void (*get_interrupt_statuses)(
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struct dpu_hw_intr *intr);
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/**
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* clear_interrupt_status - Clears HW interrupt status based on given
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* lookup IRQ index.
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* @intr: HW interrupt handle
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* @irq_idx: Lookup irq index return from irq_idx_lookup
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*/
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void (*clear_interrupt_status)(
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struct dpu_hw_intr *intr,
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int irq_idx);
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/**
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* clear_intr_status_nolock() - clears the HW interrupts without lock
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* @intr: HW interrupt handle
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* @irq_idx: Lookup irq index return from irq_idx_lookup
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*/
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void (*clear_intr_status_nolock)(
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struct dpu_hw_intr *intr,
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int irq_idx);
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/**
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* get_interrupt_status - Gets HW interrupt status, and clear if set,
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* based on given lookup IRQ index.
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* @intr: HW interrupt handle
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* @irq_idx: Lookup irq index return from irq_idx_lookup
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* @clear: True to clear irq after read
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*/
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u32 (*get_interrupt_status)(
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struct dpu_hw_intr *intr,
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int irq_idx,
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bool clear);
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/**
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* get_valid_interrupts - Gets a mask of all valid interrupt sources
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* within DPU. These are actually status bits
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* within interrupt registers that specify the
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* source of the interrupt in IRQs. For example,
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* valid interrupt sources can be MDP, DSI,
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* HDMI etc.
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* @intr: HW interrupt handle
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* @mask: Returning the interrupt source MASK
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* @return: 0 for success, otherwise failure
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*/
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int (*get_valid_interrupts)(
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struct dpu_hw_intr *intr,
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uint32_t *mask);
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};
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/**
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* struct dpu_hw_intr: hw interrupts handling data structure
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* @hw: virtual address mapping
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* @ops: function pointer mapping for IRQ handling
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* @cache_irq_mask: array of IRQ enable masks reg storage created during init
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* @save_irq_status: array of IRQ status reg storage created during init
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* @irq_idx_tbl_size: total number of irq_idx mapped in the hw_interrupts
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* @irq_lock: spinlock for accessing IRQ resources
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*/
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struct dpu_hw_intr {
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struct dpu_hw_blk_reg_map hw;
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struct dpu_hw_intr_ops ops;
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u32 *cache_irq_mask;
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u32 *save_irq_status;
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u32 irq_idx_tbl_size;
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spinlock_t irq_lock;
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};
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/**
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* dpu_hw_intr_init(): Initializes the interrupts hw object
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* @addr: mapped register io address of MDP
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* @m : pointer to mdss catalog data
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*/
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struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
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struct dpu_mdss_cfg *m);
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/**
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* dpu_hw_intr_destroy(): Cleanup interrutps hw object
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* @intr: pointer to interrupts hw object
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*/
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void dpu_hw_intr_destroy(struct dpu_hw_intr *intr);
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#endif
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