/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "dpu_hw_mdss.h"
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#include "dpu_hwio.h"
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#include "dpu_hw_catalog.h"
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#include "dpu_hw_cdm.h"
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#include "dpu_dbg.h"
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#include "dpu_kms.h"
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#define CDM_CSC_10_OPMODE 0x000
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#define CDM_CSC_10_BASE 0x004
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#define CDM_CDWN2_OP_MODE 0x100
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#define CDM_CDWN2_CLAMP_OUT 0x104
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#define CDM_CDWN2_PARAMS_3D_0 0x108
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#define CDM_CDWN2_PARAMS_3D_1 0x10C
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#define CDM_CDWN2_COEFF_COSITE_H_0 0x110
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#define CDM_CDWN2_COEFF_COSITE_H_1 0x114
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#define CDM_CDWN2_COEFF_COSITE_H_2 0x118
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#define CDM_CDWN2_COEFF_OFFSITE_H_0 0x11C
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#define CDM_CDWN2_COEFF_OFFSITE_H_1 0x120
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#define CDM_CDWN2_COEFF_OFFSITE_H_2 0x124
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#define CDM_CDWN2_COEFF_COSITE_V 0x128
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#define CDM_CDWN2_COEFF_OFFSITE_V 0x12C
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#define CDM_CDWN2_OUT_SIZE 0x130
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#define CDM_HDMI_PACK_OP_MODE 0x200
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#define CDM_CSC_10_MATRIX_COEFF_0 0x004
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/**
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* Horizontal coefficients for cosite chroma downscale
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* s13 representation of coefficients
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*/
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static u32 cosite_h_coeff[] = {0x00000016, 0x000001cc, 0x0100009e};
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/**
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* Horizontal coefficients for offsite chroma downscale
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*/
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static u32 offsite_h_coeff[] = {0x000b0005, 0x01db01eb, 0x00e40046};
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/**
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* Vertical coefficients for cosite chroma downscale
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*/
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static u32 cosite_v_coeff[] = {0x00080004};
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/**
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* Vertical coefficients for offsite chroma downscale
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*/
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static u32 offsite_v_coeff[] = {0x00060002};
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/* Limited Range rgb2yuv coeff with clamp and bias values for CSC 10 module */
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static struct dpu_csc_cfg rgb2yuv_cfg = {
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{
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0x0083, 0x0102, 0x0032,
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0x1fb5, 0x1f6c, 0x00e1,
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0x00e1, 0x1f45, 0x1fdc
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},
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{ 0x00, 0x00, 0x00 },
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{ 0x0040, 0x0200, 0x0200 },
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{ 0x000, 0x3ff, 0x000, 0x3ff, 0x000, 0x3ff },
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{ 0x040, 0x3ac, 0x040, 0x3c0, 0x040, 0x3c0 },
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};
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static struct dpu_cdm_cfg *_cdm_offset(enum dpu_cdm cdm,
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struct dpu_mdss_cfg *m,
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void __iomem *addr,
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struct dpu_hw_blk_reg_map *b)
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{
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int i;
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for (i = 0; i < m->cdm_count; i++) {
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if (cdm == m->cdm[i].id) {
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b->base_off = addr;
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b->blk_off = m->cdm[i].base;
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b->length = m->cdm[i].len;
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b->hwversion = m->hwversion;
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b->log_mask = DPU_DBG_MASK_CDM;
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return &m->cdm[i];
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}
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}
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return ERR_PTR(-EINVAL);
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}
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static int dpu_hw_cdm_setup_csc_10bit(struct dpu_hw_cdm *ctx,
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struct dpu_csc_cfg *data)
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{
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dpu_hw_csc_setup(&ctx->hw, CDM_CSC_10_MATRIX_COEFF_0, data, true);
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return 0;
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}
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static int dpu_hw_cdm_setup_cdwn(struct dpu_hw_cdm *ctx,
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struct dpu_hw_cdm_cfg *cfg)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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u32 opmode = 0;
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u32 out_size = 0;
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if (cfg->output_bit_depth == CDM_CDWN_OUTPUT_10BIT)
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opmode &= ~BIT(7);
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else
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opmode |= BIT(7);
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/* ENABLE DWNS_H bit */
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opmode |= BIT(1);
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switch (cfg->h_cdwn_type) {
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case CDM_CDWN_DISABLE:
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/* CLEAR METHOD_H field */
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opmode &= ~(0x18);
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/* CLEAR DWNS_H bit */
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opmode &= ~BIT(1);
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break;
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case CDM_CDWN_PIXEL_DROP:
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/* Clear METHOD_H field (pixel drop is 0) */
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opmode &= ~(0x18);
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break;
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case CDM_CDWN_AVG:
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/* Clear METHOD_H field (Average is 0x1) */
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opmode &= ~(0x18);
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opmode |= (0x1 << 0x3);
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break;
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case CDM_CDWN_COSITE:
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/* Clear METHOD_H field (Average is 0x2) */
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opmode &= ~(0x18);
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opmode |= (0x2 << 0x3);
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/* Co-site horizontal coefficients */
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DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_0,
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cosite_h_coeff[0]);
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DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_1,
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cosite_h_coeff[1]);
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DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_2,
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cosite_h_coeff[2]);
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break;
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case CDM_CDWN_OFFSITE:
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/* Clear METHOD_H field (Average is 0x3) */
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opmode &= ~(0x18);
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opmode |= (0x3 << 0x3);
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/* Off-site horizontal coefficients */
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DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_0,
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offsite_h_coeff[0]);
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DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_1,
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offsite_h_coeff[1]);
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DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_2,
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offsite_h_coeff[2]);
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break;
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default:
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pr_err("%s invalid horz down sampling type\n", __func__);
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return -EINVAL;
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}
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/* ENABLE DWNS_V bit */
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opmode |= BIT(2);
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switch (cfg->v_cdwn_type) {
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case CDM_CDWN_DISABLE:
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/* CLEAR METHOD_V field */
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opmode &= ~(0x60);
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/* CLEAR DWNS_V bit */
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opmode &= ~BIT(2);
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break;
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case CDM_CDWN_PIXEL_DROP:
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/* Clear METHOD_V field (pixel drop is 0) */
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opmode &= ~(0x60);
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break;
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case CDM_CDWN_AVG:
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/* Clear METHOD_V field (Average is 0x1) */
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opmode &= ~(0x60);
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opmode |= (0x1 << 0x5);
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break;
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case CDM_CDWN_COSITE:
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/* Clear METHOD_V field (Average is 0x2) */
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opmode &= ~(0x60);
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opmode |= (0x2 << 0x5);
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/* Co-site vertical coefficients */
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DPU_REG_WRITE(c,
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CDM_CDWN2_COEFF_COSITE_V,
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cosite_v_coeff[0]);
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break;
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case CDM_CDWN_OFFSITE:
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/* Clear METHOD_V field (Average is 0x3) */
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opmode &= ~(0x60);
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opmode |= (0x3 << 0x5);
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/* Off-site vertical coefficients */
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DPU_REG_WRITE(c,
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CDM_CDWN2_COEFF_OFFSITE_V,
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offsite_v_coeff[0]);
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break;
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default:
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return -EINVAL;
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}
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if (cfg->v_cdwn_type || cfg->h_cdwn_type)
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opmode |= BIT(0); /* EN CDWN module */
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else
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opmode &= ~BIT(0);
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out_size = (cfg->output_width & 0xFFFF) |
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((cfg->output_height & 0xFFFF) << 16);
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DPU_REG_WRITE(c, CDM_CDWN2_OUT_SIZE, out_size);
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DPU_REG_WRITE(c, CDM_CDWN2_OP_MODE, opmode);
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DPU_REG_WRITE(c, CDM_CDWN2_CLAMP_OUT,
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((0x3FF << 16) | 0x0));
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return 0;
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}
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static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx,
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struct dpu_hw_cdm_cfg *cdm)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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const struct dpu_format *fmt = cdm->output_fmt;
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struct cdm_output_cfg cdm_cfg = { 0 };
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u32 opmode = 0;
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u32 csc = 0;
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if (!DPU_FORMAT_IS_YUV(fmt))
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return -EINVAL;
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if (cdm->output_type == CDM_CDWN_OUTPUT_HDMI) {
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if (fmt->chroma_sample != DPU_CHROMA_H1V2)
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return -EINVAL; /*unsupported format */
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opmode = BIT(0);
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opmode |= (fmt->chroma_sample << 1);
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cdm_cfg.intf_en = true;
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}
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csc |= BIT(2);
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csc &= ~BIT(1);
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csc |= BIT(0);
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if (ctx->hw_mdp && ctx->hw_mdp->ops.setup_cdm_output)
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ctx->hw_mdp->ops.setup_cdm_output(ctx->hw_mdp, &cdm_cfg);
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DPU_REG_WRITE(c, CDM_CSC_10_OPMODE, csc);
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DPU_REG_WRITE(c, CDM_HDMI_PACK_OP_MODE, opmode);
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return 0;
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}
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static void dpu_hw_cdm_disable(struct dpu_hw_cdm *ctx)
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{
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struct cdm_output_cfg cdm_cfg = { 0 };
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if (ctx->hw_mdp && ctx->hw_mdp->ops.setup_cdm_output)
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ctx->hw_mdp->ops.setup_cdm_output(ctx->hw_mdp, &cdm_cfg);
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}
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static void _setup_cdm_ops(struct dpu_hw_cdm_ops *ops,
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unsigned long features)
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{
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ops->setup_csc_data = dpu_hw_cdm_setup_csc_10bit;
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ops->setup_cdwn = dpu_hw_cdm_setup_cdwn;
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ops->enable = dpu_hw_cdm_enable;
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ops->disable = dpu_hw_cdm_disable;
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}
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static struct dpu_hw_blk_ops dpu_hw_ops = {
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.start = NULL,
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.stop = NULL,
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};
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struct dpu_hw_cdm *dpu_hw_cdm_init(enum dpu_cdm idx,
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void __iomem *addr,
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struct dpu_mdss_cfg *m,
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struct dpu_hw_mdp *hw_mdp)
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{
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struct dpu_hw_cdm *c;
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struct dpu_cdm_cfg *cfg;
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int rc;
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c = kzalloc(sizeof(*c), GFP_KERNEL);
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if (!c)
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return ERR_PTR(-ENOMEM);
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cfg = _cdm_offset(idx, m, addr, &c->hw);
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if (IS_ERR_OR_NULL(cfg)) {
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kfree(c);
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return ERR_PTR(-EINVAL);
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}
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c->idx = idx;
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c->caps = cfg;
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_setup_cdm_ops(&c->ops, c->caps->features);
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c->hw_mdp = hw_mdp;
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rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_CDM, idx, &dpu_hw_ops);
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if (rc) {
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DPU_ERROR("failed to init hw blk %d\n", rc);
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goto blk_init_error;
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}
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/*
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* Perform any default initialization for the chroma down module
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* @setup default csc coefficients
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*/
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dpu_hw_cdm_setup_csc_10bit(c, &rgb2yuv_cfg);
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return c;
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blk_init_error:
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kzfree(c);
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return ERR_PTR(rc);
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}
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void dpu_hw_cdm_destroy(struct dpu_hw_cdm *cdm)
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{
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if (cdm)
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dpu_hw_blk_destroy(&cdm->base);
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kfree(cdm);
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}
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