/*
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* Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _DPU_CRTC_H_
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#define _DPU_CRTC_H_
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#include <linux/kthread.h>
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#include <drm/drm_crtc.h>
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#include "dpu_kms.h"
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#include "dpu_core_perf.h"
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#include "dpu_hw_blk.h"
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#define DPU_CRTC_NAME_SIZE 12
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/* define the maximum number of in-flight frame events */
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#define DPU_CRTC_FRAME_EVENT_SIZE 4
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/**
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* enum dpu_crtc_client_type: crtc client type
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* @RT_CLIENT: RealTime client like video/cmd mode display
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* voting through apps rsc
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* @NRT_CLIENT: Non-RealTime client like WB display
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* voting through apps rsc
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*/
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enum dpu_crtc_client_type {
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RT_CLIENT,
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NRT_CLIENT,
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};
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/**
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* enum dpu_crtc_smmu_state: smmu state
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* @ATTACHED: all the context banks are attached.
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* @DETACHED: all the context banks are detached.
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* @ATTACH_ALL_REQ: transient state of attaching context banks.
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* @DETACH_ALL_REQ: transient state of detaching context banks.
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*/
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enum dpu_crtc_smmu_state {
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ATTACHED = 0,
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DETACHED,
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ATTACH_ALL_REQ,
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DETACH_ALL_REQ,
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};
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/**
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* enum dpu_crtc_smmu_state_transition_type: state transition type
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* @NONE: no pending state transitions
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* @PRE_COMMIT: state transitions should be done before processing the commit
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* @POST_COMMIT: state transitions to be done after processing the commit.
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*/
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enum dpu_crtc_smmu_state_transition_type {
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NONE,
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PRE_COMMIT,
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POST_COMMIT
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};
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/**
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* struct dpu_crtc_smmu_state_data: stores the smmu state and transition type
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* @state: current state of smmu context banks
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* @transition_type: transition request type
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* @transition_error: whether there is error while transitioning the state
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*/
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struct dpu_crtc_smmu_state_data {
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uint32_t state;
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uint32_t transition_type;
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uint32_t transition_error;
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};
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/**
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* struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
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* @hw_lm: LM HW Driver context
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* @hw_ctl: CTL Path HW driver context
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* @encoder: Encoder attached to this lm & ctl
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* @mixer_op_mode: mixer blending operation mode
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* @flush_mask: mixer flush mask for ctl, mixer and pipe
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*/
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struct dpu_crtc_mixer {
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struct dpu_hw_mixer *hw_lm;
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struct dpu_hw_ctl *hw_ctl;
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struct drm_encoder *encoder;
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u32 mixer_op_mode;
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u32 flush_mask;
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};
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/**
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* struct dpu_crtc_frame_event: stores crtc frame event for crtc processing
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* @work: base work structure
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* @crtc: Pointer to crtc handling this event
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* @list: event list
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* @ts: timestamp at queue entry
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* @event: event identifier
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*/
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struct dpu_crtc_frame_event {
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struct kthread_work work;
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struct drm_crtc *crtc;
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struct list_head list;
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ktime_t ts;
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u32 event;
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};
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/*
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* Maximum number of free event structures to cache
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*/
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#define DPU_CRTC_MAX_EVENT_COUNT 16
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/**
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* struct dpu_crtc - virtualized CRTC data structure
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* @base : Base drm crtc structure
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* @name : ASCII description of this crtc
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* @num_ctls : Number of ctl paths in use
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* @num_mixers : Number of mixers in use
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* @mixers_swapped: Whether the mixers have been swapped for left/right update
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* especially in the case of DSC Merge.
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* @mixers : List of active mixers
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* @event : Pointer to last received drm vblank event. If there is a
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* pending vblank event, this will be non-null.
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* @vsync_count : Running count of received vsync events
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* @drm_requested_vblank : Whether vblanks have been enabled in the encoder
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* @property_info : Opaque structure for generic property support
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* @property_defaults : Array of default values for generic property support
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* @stage_cfg : H/w mixer stage configuration
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* @debugfs_root : Parent of debugfs node
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* @vblank_cb_count : count of vblank callback since last reset
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* @play_count : frame count between crtc enable and disable
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* @vblank_cb_time : ktime at vblank count reset
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* @vblank_requested : whether the user has requested vblank events
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* @suspend : whether or not a suspend operation is in progress
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* @enabled : whether the DPU CRTC is currently enabled. updated in the
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* commit-thread, not state-swap time which is earlier, so
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* safe to make decisions on during VBLANK on/off work
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* @feature_list : list of color processing features supported on a crtc
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* @active_list : list of color processing features are active
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* @dirty_list : list of color processing features are dirty
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* @ad_dirty: list containing ad properties that are dirty
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* @ad_active: list containing ad properties that are active
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* @crtc_lock : crtc lock around create, destroy and access.
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* @frame_pending : Whether or not an update is pending
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* @frame_events : static allocation of in-flight frame events
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* @frame_event_list : available frame event list
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* @spin_lock : spin lock for frame event, transaction status, etc...
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* @frame_done_comp : for frame_event_done synchronization
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* @event_thread : Pointer to event handler thread
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* @event_worker : Event worker queue
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* @event_lock : Spinlock around event handling code
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* @misr_enable : boolean entry indicates misr enable/disable status.
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* @misr_frame_count : misr frame count provided by client
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* @misr_data : store misr data before turning off the clocks.
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* @phandle: Pointer to power handler
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* @power_event : registered power event handle
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* @cur_perf : current performance committed to clock/bandwidth driver
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* @rp_lock : serialization lock for resource pool
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* @rp_head : list of active resource pool
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* @scl3_cfg_lut : qseed3 lut config
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*/
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struct dpu_crtc {
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struct drm_crtc base;
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char name[DPU_CRTC_NAME_SIZE];
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/* HW Resources reserved for the crtc */
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u32 num_ctls;
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u32 num_mixers;
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bool mixers_swapped;
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struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
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struct dpu_hw_scaler3_lut_cfg *scl3_lut_cfg;
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struct drm_pending_vblank_event *event;
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u32 vsync_count;
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struct dpu_hw_stage_cfg stage_cfg;
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struct dentry *debugfs_root;
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u32 vblank_cb_count;
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u64 play_count;
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ktime_t vblank_cb_time;
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bool vblank_requested;
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bool suspend;
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bool enabled;
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struct list_head feature_list;
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struct list_head active_list;
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struct list_head dirty_list;
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struct list_head ad_dirty;
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struct list_head ad_active;
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struct mutex crtc_lock;
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atomic_t frame_pending;
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struct dpu_crtc_frame_event frame_events[DPU_CRTC_FRAME_EVENT_SIZE];
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struct list_head frame_event_list;
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spinlock_t spin_lock;
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struct completion frame_done_comp;
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/* for handling internal event thread */
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spinlock_t event_lock;
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bool misr_enable;
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u32 misr_frame_count;
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u32 misr_data[CRTC_DUAL_MIXERS];
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struct dpu_power_handle *phandle;
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struct dpu_power_event *power_event;
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struct dpu_core_perf_params cur_perf;
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struct mutex rp_lock;
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struct list_head rp_head;
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struct dpu_crtc_smmu_state_data smmu_state;
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};
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#define to_dpu_crtc(x) container_of(x, struct dpu_crtc, base)
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/**
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* struct dpu_crtc_res_ops - common operations for crtc resources
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* @get: get given resource
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* @put: put given resource
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*/
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struct dpu_crtc_res_ops {
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void *(*get)(void *val, u32 type, u64 tag);
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void (*put)(void *val);
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};
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#define DPU_CRTC_RES_FLAG_FREE BIT(0)
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/**
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* struct dpu_crtc_res - definition of crtc resources
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* @list: list of crtc resource
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* @type: crtc resource type
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* @tag: unique identifier per type
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* @refcount: reference/usage count
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* @ops: callback operations
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* @val: resource handle associated with type/tag
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* @flags: customization flags
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*/
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struct dpu_crtc_res {
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struct list_head list;
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u32 type;
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u64 tag;
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atomic_t refcount;
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struct dpu_crtc_res_ops ops;
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void *val;
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u32 flags;
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};
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/**
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* dpu_crtc_respool - crtc resource pool
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* @rp_lock: pointer to serialization lock
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* @rp_head: pointer to head of active resource pools of this crtc
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* @rp_list: list of crtc resource pool
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* @sequence_id: sequence identifier, incremented per state duplication
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* @res_list: list of resource managed by this resource pool
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* @ops: resource operations for parent resource pool
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*/
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struct dpu_crtc_respool {
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struct mutex *rp_lock;
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struct list_head *rp_head;
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struct list_head rp_list;
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u32 sequence_id;
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struct list_head res_list;
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struct dpu_crtc_res_ops ops;
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};
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/**
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* struct dpu_crtc_state - dpu container for atomic crtc state
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* @base: Base drm crtc state structure
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* @is_ppsplit : Whether current topology requires PPSplit special handling
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* @bw_control : true if bw/clk controlled by core bw/clk properties
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* @bw_split_vote : true if bw controlled by llcc/dram bw properties
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* @lm_bounds : LM boundaries based on current mode full resolution, no ROI.
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* Origin top left of CRTC.
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* @property_state: Local storage for msm_prop properties
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* @property_values: Current crtc property values
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* @input_fence_timeout_ns : Cached input fence timeout, in ns
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* @new_perf: new performance state being requested
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*/
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struct dpu_crtc_state {
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struct drm_crtc_state base;
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bool bw_control;
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bool bw_split_vote;
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bool is_ppsplit;
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struct drm_rect lm_bounds[CRTC_DUAL_MIXERS];
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uint64_t input_fence_timeout_ns;
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struct dpu_core_perf_params new_perf;
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struct dpu_crtc_respool rp;
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};
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#define to_dpu_crtc_state(x) \
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container_of(x, struct dpu_crtc_state, base)
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/**
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* dpu_crtc_get_mixer_width - get the mixer width
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* Mixer width will be same as panel width(/2 for split)
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*/
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static inline int dpu_crtc_get_mixer_width(struct dpu_crtc *dpu_crtc,
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struct dpu_crtc_state *cstate, struct drm_display_mode *mode)
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{
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u32 mixer_width;
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if (!dpu_crtc || !cstate || !mode)
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return 0;
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mixer_width = (dpu_crtc->num_mixers == CRTC_DUAL_MIXERS ?
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mode->hdisplay / CRTC_DUAL_MIXERS : mode->hdisplay);
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return mixer_width;
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}
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/**
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* dpu_crtc_get_mixer_height - get the mixer height
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* Mixer height will be same as panel height
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*/
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static inline int dpu_crtc_get_mixer_height(struct dpu_crtc *dpu_crtc,
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struct dpu_crtc_state *cstate, struct drm_display_mode *mode)
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{
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if (!dpu_crtc || !cstate || !mode)
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return 0;
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return mode->vdisplay;
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}
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/**
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* dpu_crtc_frame_pending - retun the number of pending frames
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* @crtc: Pointer to drm crtc object
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*/
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static inline int dpu_crtc_frame_pending(struct drm_crtc *crtc)
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{
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struct dpu_crtc *dpu_crtc;
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if (!crtc)
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return -EINVAL;
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dpu_crtc = to_dpu_crtc(crtc);
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return atomic_read(&dpu_crtc->frame_pending);
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}
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/**
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* dpu_crtc_vblank - enable or disable vblanks for this crtc
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* @crtc: Pointer to drm crtc object
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* @en: true to enable vblanks, false to disable
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*/
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int dpu_crtc_vblank(struct drm_crtc *crtc, bool en);
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/**
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* dpu_crtc_commit_kickoff - trigger kickoff of the commit for this crtc
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* @crtc: Pointer to drm crtc object
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*/
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void dpu_crtc_commit_kickoff(struct drm_crtc *crtc);
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/**
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* dpu_crtc_complete_commit - callback signalling completion of current commit
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* @crtc: Pointer to drm crtc object
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* @old_state: Pointer to drm crtc old state object
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*/
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void dpu_crtc_complete_commit(struct drm_crtc *crtc,
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struct drm_crtc_state *old_state);
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/**
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* dpu_crtc_init - create a new crtc object
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* @dev: dpu device
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* @plane: base plane
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* @Return: new crtc object or error
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*/
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struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane);
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/**
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* dpu_crtc_register_custom_event - api for enabling/disabling crtc event
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* @kms: Pointer to dpu_kms
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* @crtc_drm: Pointer to crtc object
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* @event: Event that client is interested
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* @en: Flag to enable/disable the event
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*/
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int dpu_crtc_register_custom_event(struct dpu_kms *kms,
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struct drm_crtc *crtc_drm, u32 event, bool en);
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/**
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* dpu_crtc_get_intf_mode - get interface mode of the given crtc
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* @crtc: Pointert to crtc
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*/
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enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc);
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/**
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* dpu_crtc_get_client_type - check the crtc type- rt, nrt etc.
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* @crtc: Pointer to crtc
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*/
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static inline enum dpu_crtc_client_type dpu_crtc_get_client_type(
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struct drm_crtc *crtc)
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{
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struct dpu_crtc_state *cstate =
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crtc ? to_dpu_crtc_state(crtc->state) : NULL;
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if (!cstate)
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return NRT_CLIENT;
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return RT_CLIENT;
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}
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/**
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* dpu_crtc_is_enabled - check if dpu crtc is enabled or not
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* @crtc: Pointer to crtc
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*/
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static inline bool dpu_crtc_is_enabled(struct drm_crtc *crtc)
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{
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return crtc ? crtc->enabled : false;
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}
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#endif /* _DPU_CRTC_H_ */
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