/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
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#include <linux/debugfs.h>
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#include <linux/errno.h>
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#include <linux/mutex.h>
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#include <linux/sort.h>
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#include <linux/clk.h>
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#include <linux/bitmap.h>
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#include "dpu_kms.h"
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#include "dpu_trace.h"
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#include "dpu_crtc.h"
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#include "dpu_core_perf.h"
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#define DPU_PERF_MODE_STRING_SIZE 128
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/**
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* enum dpu_perf_mode - performance tuning mode
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* @DPU_PERF_MODE_NORMAL: performance controlled by user mode client
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* @DPU_PERF_MODE_MINIMUM: performance bounded by minimum setting
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* @DPU_PERF_MODE_FIXED: performance bounded by fixed setting
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*/
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enum dpu_perf_mode {
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DPU_PERF_MODE_NORMAL,
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DPU_PERF_MODE_MINIMUM,
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DPU_PERF_MODE_FIXED,
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DPU_PERF_MODE_MAX
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};
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static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
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{
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struct msm_drm_private *priv;
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if (!crtc->dev || !crtc->dev->dev_private) {
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DPU_ERROR("invalid device\n");
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return NULL;
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}
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priv = crtc->dev->dev_private;
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if (!priv || !priv->kms) {
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DPU_ERROR("invalid kms\n");
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return NULL;
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}
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return to_dpu_kms(priv->kms);
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}
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static bool _dpu_core_perf_crtc_is_power_on(struct drm_crtc *crtc)
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{
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return dpu_crtc_is_enabled(crtc);
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}
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static bool _dpu_core_video_mode_intf_connected(struct drm_crtc *crtc)
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{
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struct drm_crtc *tmp_crtc;
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bool intf_connected = false;
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if (!crtc)
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goto end;
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drm_for_each_crtc(tmp_crtc, crtc->dev) {
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if ((dpu_crtc_get_intf_mode(tmp_crtc) == INTF_MODE_VIDEO) &&
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_dpu_core_perf_crtc_is_power_on(tmp_crtc)) {
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DPU_DEBUG("video interface connected crtc:%d\n",
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tmp_crtc->base.id);
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intf_connected = true;
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goto end;
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}
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}
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end:
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return intf_connected;
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}
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static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
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struct drm_crtc *crtc,
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struct drm_crtc_state *state,
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struct dpu_core_perf_params *perf)
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{
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struct dpu_crtc_state *dpu_cstate;
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int i;
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if (!kms || !kms->catalog || !crtc || !state || !perf) {
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DPU_ERROR("invalid parameters\n");
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return;
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}
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dpu_cstate = to_dpu_crtc_state(state);
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memset(perf, 0, sizeof(struct dpu_core_perf_params));
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if (!dpu_cstate->bw_control) {
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for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
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perf->bw_ctl[i] = kms->catalog->perf.max_bw_high *
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1000ULL;
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perf->max_per_pipe_ib[i] = perf->bw_ctl[i];
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}
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perf->core_clk_rate = kms->perf.max_core_clk_rate;
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} else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
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for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
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perf->bw_ctl[i] = 0;
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perf->max_per_pipe_ib[i] = 0;
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}
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perf->core_clk_rate = 0;
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} else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) {
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for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
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perf->bw_ctl[i] = kms->perf.fix_core_ab_vote;
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perf->max_per_pipe_ib[i] = kms->perf.fix_core_ib_vote;
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}
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perf->core_clk_rate = kms->perf.fix_core_clk_rate;
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}
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DPU_DEBUG(
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"crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu llcc_ib=%llu llcc_ab=%llu mem_ib=%llu mem_ab=%llu\n",
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crtc->base.id, perf->core_clk_rate,
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perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MNOC],
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perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC],
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perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC],
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perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC],
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perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI],
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perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI]);
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}
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int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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u32 bw, threshold;
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u64 bw_sum_of_intfs = 0;
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enum dpu_crtc_client_type curr_client_type;
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bool is_video_mode;
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struct dpu_crtc_state *dpu_cstate;
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struct drm_crtc *tmp_crtc;
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struct dpu_kms *kms;
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int i;
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if (!crtc || !state) {
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DPU_ERROR("invalid crtc\n");
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return -EINVAL;
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}
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kms = _dpu_crtc_get_kms(crtc);
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if (!kms || !kms->catalog) {
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DPU_ERROR("invalid parameters\n");
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return 0;
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}
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/* we only need bandwidth check on real-time clients (interfaces) */
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if (dpu_crtc_get_client_type(crtc) == NRT_CLIENT)
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return 0;
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dpu_cstate = to_dpu_crtc_state(state);
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/* obtain new values */
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_dpu_core_perf_calc_crtc(kms, crtc, state, &dpu_cstate->new_perf);
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for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC;
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i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
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bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl[i];
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curr_client_type = dpu_crtc_get_client_type(crtc);
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drm_for_each_crtc(tmp_crtc, crtc->dev) {
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if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) &&
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(dpu_crtc_get_client_type(tmp_crtc) ==
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curr_client_type) &&
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(tmp_crtc != crtc)) {
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struct dpu_crtc_state *tmp_cstate =
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to_dpu_crtc_state(tmp_crtc->state);
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DPU_DEBUG("crtc:%d bw:%llu ctrl:%d\n",
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tmp_crtc->base.id,
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tmp_cstate->new_perf.bw_ctl[i],
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tmp_cstate->bw_control);
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/*
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* For bw check only use the bw if the
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* atomic property has been already set
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*/
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if (tmp_cstate->bw_control)
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bw_sum_of_intfs +=
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tmp_cstate->new_perf.bw_ctl[i];
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}
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}
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/* convert bandwidth to kb */
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bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000);
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DPU_DEBUG("calculated bandwidth=%uk\n", bw);
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is_video_mode = dpu_crtc_get_intf_mode(crtc) == INTF_MODE_VIDEO;
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threshold = (is_video_mode ||
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_dpu_core_video_mode_intf_connected(crtc)) ?
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kms->catalog->perf.max_bw_low :
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kms->catalog->perf.max_bw_high;
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DPU_DEBUG("final threshold bw limit = %d\n", threshold);
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if (!dpu_cstate->bw_control) {
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DPU_DEBUG("bypass bandwidth check\n");
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} else if (!threshold) {
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DPU_ERROR("no bandwidth limits specified\n");
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return -E2BIG;
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} else if (bw > threshold) {
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DPU_ERROR("exceeds bandwidth: %ukb > %ukb\n", bw,
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threshold);
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return -E2BIG;
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}
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}
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return 0;
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}
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static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms,
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struct drm_crtc *crtc, u32 bus_id)
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{
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struct dpu_core_perf_params perf = { { 0 } };
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enum dpu_crtc_client_type curr_client_type
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= dpu_crtc_get_client_type(crtc);
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struct drm_crtc *tmp_crtc;
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struct dpu_crtc_state *dpu_cstate;
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int ret = 0;
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drm_for_each_crtc(tmp_crtc, crtc->dev) {
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if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) &&
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curr_client_type ==
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dpu_crtc_get_client_type(tmp_crtc)) {
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dpu_cstate = to_dpu_crtc_state(tmp_crtc->state);
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perf.max_per_pipe_ib[bus_id] =
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max(perf.max_per_pipe_ib[bus_id],
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dpu_cstate->new_perf.max_per_pipe_ib[bus_id]);
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DPU_DEBUG("crtc=%d bus_id=%d bw=%llu\n",
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tmp_crtc->base.id, bus_id,
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dpu_cstate->new_perf.bw_ctl[bus_id]);
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}
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}
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return ret;
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}
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/**
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* @dpu_core_perf_crtc_release_bw() - request zero bandwidth
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* @crtc - pointer to a crtc
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*
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* Function checks a state variable for the crtc, if all pending commit
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* requests are done, meaning no more bandwidth is needed, release
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* bandwidth request.
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*/
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void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc)
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{
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struct drm_crtc *tmp_crtc;
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struct dpu_crtc *dpu_crtc;
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struct dpu_crtc_state *dpu_cstate;
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struct dpu_kms *kms;
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int i;
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if (!crtc) {
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DPU_ERROR("invalid crtc\n");
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return;
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}
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kms = _dpu_crtc_get_kms(crtc);
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if (!kms || !kms->catalog) {
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DPU_ERROR("invalid kms\n");
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return;
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}
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dpu_crtc = to_dpu_crtc(crtc);
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dpu_cstate = to_dpu_crtc_state(crtc->state);
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/* only do this for command mode rt client */
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if (dpu_crtc_get_intf_mode(crtc) != INTF_MODE_CMD)
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return;
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/*
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* If video interface present, cmd panel bandwidth cannot be
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* released.
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*/
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if (dpu_crtc_get_intf_mode(crtc) == INTF_MODE_CMD)
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drm_for_each_crtc(tmp_crtc, crtc->dev) {
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if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) &&
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dpu_crtc_get_intf_mode(tmp_crtc) ==
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INTF_MODE_VIDEO)
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return;
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}
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/* Release the bandwidth */
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if (kms->perf.enable_bw_release) {
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trace_dpu_cmd_release_bw(crtc->base.id);
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DPU_DEBUG("Release BW crtc=%d\n", crtc->base.id);
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for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
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dpu_crtc->cur_perf.bw_ctl[i] = 0;
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_dpu_core_perf_crtc_update_bus(kms, crtc, i);
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}
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}
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}
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static int _dpu_core_perf_set_core_clk_rate(struct dpu_kms *kms, u64 rate)
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{
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struct dss_clk *core_clk = kms->perf.core_clk;
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if (core_clk->max_rate && (rate > core_clk->max_rate))
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rate = core_clk->max_rate;
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core_clk->rate = rate;
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return msm_dss_clk_set_rate(core_clk, 1);
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}
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static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms)
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{
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u64 clk_rate = kms->perf.perf_tune.min_core_clk;
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struct drm_crtc *crtc;
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struct dpu_crtc_state *dpu_cstate;
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drm_for_each_crtc(crtc, kms->dev) {
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if (_dpu_core_perf_crtc_is_power_on(crtc)) {
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dpu_cstate = to_dpu_crtc_state(crtc->state);
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clk_rate = max(dpu_cstate->new_perf.core_clk_rate,
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clk_rate);
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clk_rate = clk_round_rate(kms->perf.core_clk->clk,
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clk_rate);
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}
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}
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if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED)
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clk_rate = kms->perf.fix_core_clk_rate;
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DPU_DEBUG("clk:%llu\n", clk_rate);
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return clk_rate;
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}
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int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
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int params_changed, bool stop_req)
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{
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struct dpu_core_perf_params *new, *old;
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int update_bus = 0, update_clk = 0;
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u64 clk_rate = 0;
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struct dpu_crtc *dpu_crtc;
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struct dpu_crtc_state *dpu_cstate;
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int i;
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struct msm_drm_private *priv;
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struct dpu_kms *kms;
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int ret;
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if (!crtc) {
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DPU_ERROR("invalid crtc\n");
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return -EINVAL;
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}
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kms = _dpu_crtc_get_kms(crtc);
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if (!kms || !kms->catalog) {
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DPU_ERROR("invalid kms\n");
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return -EINVAL;
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}
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priv = kms->dev->dev_private;
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dpu_crtc = to_dpu_crtc(crtc);
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dpu_cstate = to_dpu_crtc_state(crtc->state);
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DPU_DEBUG("crtc:%d stop_req:%d core_clk:%llu\n",
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crtc->base.id, stop_req, kms->perf.core_clk_rate);
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old = &dpu_crtc->cur_perf;
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new = &dpu_cstate->new_perf;
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if (_dpu_core_perf_crtc_is_power_on(crtc) && !stop_req) {
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for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
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/*
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* cases for bus bandwidth update.
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* 1. new bandwidth vote - "ab or ib vote" is higher
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* than current vote for update request.
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* 2. new bandwidth vote - "ab or ib vote" is lower
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* than current vote at end of commit or stop.
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*/
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if ((params_changed && ((new->bw_ctl[i] >
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old->bw_ctl[i]) ||
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(new->max_per_pipe_ib[i] >
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old->max_per_pipe_ib[i]))) ||
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(!params_changed && ((new->bw_ctl[i] <
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old->bw_ctl[i]) ||
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(new->max_per_pipe_ib[i] <
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old->max_per_pipe_ib[i])))) {
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DPU_DEBUG(
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"crtc=%d p=%d new_bw=%llu,old_bw=%llu\n",
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crtc->base.id, params_changed,
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new->bw_ctl[i], old->bw_ctl[i]);
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old->bw_ctl[i] = new->bw_ctl[i];
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old->max_per_pipe_ib[i] =
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new->max_per_pipe_ib[i];
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update_bus |= BIT(i);
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}
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}
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if ((params_changed &&
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(new->core_clk_rate > old->core_clk_rate)) ||
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(!params_changed &&
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(new->core_clk_rate < old->core_clk_rate))) {
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old->core_clk_rate = new->core_clk_rate;
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update_clk = 1;
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}
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} else {
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DPU_DEBUG("crtc=%d disable\n", crtc->base.id);
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memset(old, 0, sizeof(*old));
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memset(new, 0, sizeof(*new));
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update_bus = ~0;
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update_clk = 1;
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}
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trace_dpu_perf_crtc_update(crtc->base.id,
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new->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC],
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new->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC],
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new->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI],
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new->core_clk_rate, stop_req,
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update_bus, update_clk);
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for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
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if (update_bus & BIT(i)) {
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ret = _dpu_core_perf_crtc_update_bus(kms, crtc, i);
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if (ret) {
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DPU_ERROR("crtc-%d: failed to update bw vote for bus-%d\n",
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crtc->base.id, i);
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return ret;
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}
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}
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}
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/*
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* Update the clock after bandwidth vote to ensure
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* bandwidth is available before clock rate is increased.
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*/
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if (update_clk) {
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clk_rate = _dpu_core_perf_get_core_clk_rate(kms);
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trace_dpu_core_perf_update_clk(kms->dev, stop_req, clk_rate);
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ret = _dpu_core_perf_set_core_clk_rate(kms, clk_rate);
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if (ret) {
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DPU_ERROR("failed to set %s clock rate %llu\n",
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kms->perf.core_clk->clk_name, clk_rate);
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return ret;
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}
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kms->perf.core_clk_rate = clk_rate;
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DPU_DEBUG("update clk rate = %lld HZ\n", clk_rate);
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}
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return 0;
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}
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#ifdef CONFIG_DEBUG_FS
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static ssize_t _dpu_core_perf_mode_write(struct file *file,
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const char __user *user_buf, size_t count, loff_t *ppos)
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{
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struct dpu_core_perf *perf = file->private_data;
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struct dpu_perf_cfg *cfg = &perf->catalog->perf;
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u32 perf_mode = 0;
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char buf[10];
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if (!perf)
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return -ENODEV;
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if (count >= sizeof(buf))
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return -EFAULT;
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if (copy_from_user(buf, user_buf, count))
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return -EFAULT;
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buf[count] = 0; /* end of string */
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if (kstrtouint(buf, 0, &perf_mode))
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return -EFAULT;
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if (perf_mode >= DPU_PERF_MODE_MAX)
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return -EFAULT;
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if (perf_mode == DPU_PERF_MODE_FIXED) {
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DRM_INFO("fix performance mode\n");
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} else if (perf_mode == DPU_PERF_MODE_MINIMUM) {
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/* run the driver with max clk and BW vote */
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perf->perf_tune.min_core_clk = perf->max_core_clk_rate;
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perf->perf_tune.min_bus_vote =
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(u64) cfg->max_bw_high * 1000;
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DRM_INFO("minimum performance mode\n");
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} else if (perf_mode == DPU_PERF_MODE_NORMAL) {
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/* reset the perf tune params to 0 */
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perf->perf_tune.min_core_clk = 0;
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perf->perf_tune.min_bus_vote = 0;
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DRM_INFO("normal performance mode\n");
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}
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perf->perf_tune.mode = perf_mode;
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return count;
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}
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static ssize_t _dpu_core_perf_mode_read(struct file *file,
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char __user *buff, size_t count, loff_t *ppos)
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{
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struct dpu_core_perf *perf = file->private_data;
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int len = 0;
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char buf[DPU_PERF_MODE_STRING_SIZE] = {'\0'};
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if (!perf)
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return -ENODEV;
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if (*ppos)
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return 0; /* the end */
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len = snprintf(buf, sizeof(buf),
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"mode %d min_mdp_clk %llu min_bus_vote %llu\n",
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perf->perf_tune.mode,
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perf->perf_tune.min_core_clk,
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perf->perf_tune.min_bus_vote);
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if (len < 0 || len >= sizeof(buf))
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return 0;
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if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
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return -EFAULT;
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*ppos += len; /* increase offset */
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return len;
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}
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static const struct file_operations dpu_core_perf_mode_fops = {
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.open = simple_open,
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.read = _dpu_core_perf_mode_read,
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.write = _dpu_core_perf_mode_write,
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};
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static void dpu_core_perf_debugfs_destroy(struct dpu_core_perf *perf)
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{
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debugfs_remove_recursive(perf->debugfs_root);
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perf->debugfs_root = NULL;
|
}
|
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int dpu_core_perf_debugfs_init(struct dpu_core_perf *perf,
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struct dentry *parent)
|
{
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struct dpu_mdss_cfg *catalog = perf->catalog;
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struct msm_drm_private *priv;
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struct dpu_kms *dpu_kms;
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priv = perf->dev->dev_private;
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if (!priv || !priv->kms) {
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DPU_ERROR("invalid KMS reference\n");
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return -EINVAL;
|
}
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dpu_kms = to_dpu_kms(priv->kms);
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perf->debugfs_root = debugfs_create_dir("core_perf", parent);
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if (!perf->debugfs_root) {
|
DPU_ERROR("failed to create core perf debugfs\n");
|
return -EINVAL;
|
}
|
|
debugfs_create_u64("max_core_clk_rate", 0600, perf->debugfs_root,
|
&perf->max_core_clk_rate);
|
debugfs_create_u64("core_clk_rate", 0600, perf->debugfs_root,
|
&perf->core_clk_rate);
|
debugfs_create_u32("enable_bw_release", 0600, perf->debugfs_root,
|
(u32 *)&perf->enable_bw_release);
|
debugfs_create_u32("threshold_low", 0600, perf->debugfs_root,
|
(u32 *)&catalog->perf.max_bw_low);
|
debugfs_create_u32("threshold_high", 0600, perf->debugfs_root,
|
(u32 *)&catalog->perf.max_bw_high);
|
debugfs_create_u32("min_core_ib", 0600, perf->debugfs_root,
|
(u32 *)&catalog->perf.min_core_ib);
|
debugfs_create_u32("min_llcc_ib", 0600, perf->debugfs_root,
|
(u32 *)&catalog->perf.min_llcc_ib);
|
debugfs_create_u32("min_dram_ib", 0600, perf->debugfs_root,
|
(u32 *)&catalog->perf.min_dram_ib);
|
debugfs_create_file("perf_mode", 0600, perf->debugfs_root,
|
(u32 *)perf, &dpu_core_perf_mode_fops);
|
debugfs_create_u64("fix_core_clk_rate", 0600, perf->debugfs_root,
|
&perf->fix_core_clk_rate);
|
debugfs_create_u64("fix_core_ib_vote", 0600, perf->debugfs_root,
|
&perf->fix_core_ib_vote);
|
debugfs_create_u64("fix_core_ab_vote", 0600, perf->debugfs_root,
|
&perf->fix_core_ab_vote);
|
|
return 0;
|
}
|
#else
|
static void dpu_core_perf_debugfs_destroy(struct dpu_core_perf *perf)
|
{
|
}
|
|
int dpu_core_perf_debugfs_init(struct dpu_core_perf *perf,
|
struct dentry *parent)
|
{
|
return 0;
|
}
|
#endif
|
|
void dpu_core_perf_destroy(struct dpu_core_perf *perf)
|
{
|
if (!perf) {
|
DPU_ERROR("invalid parameters\n");
|
return;
|
}
|
|
dpu_core_perf_debugfs_destroy(perf);
|
perf->max_core_clk_rate = 0;
|
perf->core_clk = NULL;
|
perf->phandle = NULL;
|
perf->catalog = NULL;
|
perf->dev = NULL;
|
}
|
|
int dpu_core_perf_init(struct dpu_core_perf *perf,
|
struct drm_device *dev,
|
struct dpu_mdss_cfg *catalog,
|
struct dpu_power_handle *phandle,
|
struct dss_clk *core_clk)
|
{
|
perf->dev = dev;
|
perf->catalog = catalog;
|
perf->phandle = phandle;
|
perf->core_clk = core_clk;
|
|
perf->max_core_clk_rate = core_clk->max_rate;
|
if (!perf->max_core_clk_rate) {
|
DPU_DEBUG("optional max core clk rate, use default\n");
|
perf->max_core_clk_rate = DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE;
|
}
|
|
return 0;
|
}
|
