/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2017 The Linux Foundation. All rights reserved. */
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#ifndef _A6XX_HFI_H_
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#define _A6XX_HFI_H_
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struct a6xx_hfi_queue_table_header {
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u32 version;
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u32 size; /* Size of the queue table in dwords */
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u32 qhdr0_offset; /* Offset of the first queue header */
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u32 qhdr_size; /* Size of the queue headers */
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u32 num_queues; /* Number of total queues */
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u32 active_queues; /* Number of active queues */
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};
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struct a6xx_hfi_queue_header {
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u32 status;
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u32 iova;
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u32 type;
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u32 size;
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u32 msg_size;
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u32 dropped;
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u32 rx_watermark;
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u32 tx_watermark;
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u32 rx_request;
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u32 tx_request;
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u32 read_index;
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u32 write_index;
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};
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struct a6xx_hfi_queue {
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struct a6xx_hfi_queue_header *header;
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spinlock_t lock;
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u32 *data;
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atomic_t seqnum;
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};
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/* This is the outgoing queue to the GMU */
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#define HFI_COMMAND_QUEUE 0
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/* THis is the incoming response queue from the GMU */
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#define HFI_RESPONSE_QUEUE 1
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#define HFI_HEADER_ID(msg) ((msg) & 0xff)
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#define HFI_HEADER_SIZE(msg) (((msg) >> 8) & 0xff)
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#define HFI_HEADER_SEQNUM(msg) (((msg) >> 20) & 0xfff)
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/* FIXME: Do we need this or can we use ARRAY_SIZE? */
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#define HFI_RESPONSE_PAYLOAD_SIZE 16
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/* HFI message types */
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#define HFI_MSG_CMD 0
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#define HFI_MSG_ACK 2
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#define HFI_F2H_MSG_ACK 126
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struct a6xx_hfi_msg_response {
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u32 header;
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u32 ret_header;
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u32 error;
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u32 payload[HFI_RESPONSE_PAYLOAD_SIZE];
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};
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#define HFI_F2H_MSG_ERROR 100
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struct a6xx_hfi_msg_error {
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u32 header;
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u32 code;
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u32 payload[2];
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};
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#define HFI_H2F_MSG_INIT 0
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struct a6xx_hfi_msg_gmu_init_cmd {
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u32 header;
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u32 seg_id;
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u32 dbg_buffer_addr;
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u32 dbg_buffer_size;
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u32 boot_state;
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};
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#define HFI_H2F_MSG_FW_VERSION 1
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struct a6xx_hfi_msg_fw_version {
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u32 header;
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u32 supported_version;
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};
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#define HFI_H2F_MSG_PERF_TABLE 4
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struct perf_level {
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u32 vote;
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u32 freq;
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};
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struct a6xx_hfi_msg_perf_table {
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u32 header;
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u32 num_gpu_levels;
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u32 num_gmu_levels;
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struct perf_level gx_votes[16];
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struct perf_level cx_votes[4];
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};
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#define HFI_H2F_MSG_BW_TABLE 3
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struct a6xx_hfi_msg_bw_table {
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u32 header;
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u32 bw_level_num;
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u32 cnoc_cmds_num;
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u32 ddr_cmds_num;
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u32 cnoc_wait_bitmask;
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u32 ddr_wait_bitmask;
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u32 cnoc_cmds_addrs[6];
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u32 cnoc_cmds_data[2][6];
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u32 ddr_cmds_addrs[8];
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u32 ddr_cmds_data[16][8];
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};
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#define HFI_H2F_MSG_TEST 5
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struct a6xx_hfi_msg_test {
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u32 header;
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};
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#endif
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