// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 Rockchip Electronics Co. Ltd.
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*
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* Author: Wyon Bi <bivvy.bi@rock-chips.com>
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/gpio/consumer.h>
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#include <linux/regulator/consumer.h>
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#include <linux/i2c.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/regmap.h>
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#include <drm/drmP.h>
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#include <drm/drm_of.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_panel.h>
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#include <drm/drm_mipi_dsi.h>
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#define VENDOR_ID 0x0000
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#define DEVICE_ID_H 0x0001
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#define DEVICE_ID_L 0x0002
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#define VERSION_ID 0x0003
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#define FIRMWARE_VERSION 0x0008
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#define CONFIG_FINISH 0x0009
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#define PD_CTRL_0 0x000a
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#define PD_CTRL_1 0x000b
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#define PD_CTRL_2 0x000c
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#define PD_CTRL_3 0x000d
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#define RST_CTRL_0 0x000e
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#define RST_CTRL_1 0x000f
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#define SYS_CTRL_0 0x0010
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#define SYS_CTRL_1 0x0011
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#define SYS_CTRL_2 0x0012
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#define SYS_CTRL_3 0x0013
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#define SYS_CTRL_4 0x0014
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#define RGB_DRV_0 0x0018
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#define RGB_DRV_1 0x0019
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#define RGB_DRV_2 0x001a
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#define RGB_DRV_3 0x001b
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#define RGB_DLY_0 0x001c
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#define RGB_DLY_1 0x001d
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#define RGB_TEST_CTRL 0x001e
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#define ATE_PLL_EN 0x001f
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#define HACTIVE_L 0x0020
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#define VACTIVE_L 0x0021
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#define VACTIVE_HACTIVE_H 0x0022
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#define HFP_L 0x0023
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#define HSW_L 0x0024
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#define HBP_L 0x0025
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#define HFP_HSW_HBP_H 0x0026
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#define VFP 0x0027
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#define VSW 0x0028
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#define VBP 0x0029
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#define BIST_POL 0x002a
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#define BIST_RED 0x002b
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#define BIST_GREEN 0x002c
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#define BIST_BLUE 0x002d
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#define BIST_CHESS_X 0x002e
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#define BIST_CHESS_Y 0x002f
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#define BIST_CHESS_XY_H 0x0030
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#define BIST_FRAME_TIME_L 0x0031
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#define BIST_FRAME_TIME_H 0x0032
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#define FIFO_MAX_ADDR_LOW 0x0033
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#define SYNC_EVENT_DLY_LOW 0x0034
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#define HSW_MIN 0x0035
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#define HFP_MIN 0x0036
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#define LOGIC_RST_NUM 0x0037
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#define OSC_CTRL_0 0x0048
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#define OSC_CTRL_1 0x0049
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#define OSC_CTRL_2 0x004a
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#define OSC_CTRL_3 0x004b
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#define OSC_CTRL_4 0x004c
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#define OSC_CTRL_5 0x004d
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#define BG_CTRL 0x004e
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#define LDO_PLL 0x004f
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#define PLL_CTRL_0 0x0050
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#define PLL_CTRL_1 0x0051
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#define PLL_CTRL_2 0x0052
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#define PLL_CTRL_3 0x0053
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#define PLL_CTRL_4 0x0054
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#define PLL_CTRL_5 0x0055
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#define PLL_CTRL_6 0x0056
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#define PLL_CTRL_7 0x0057
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#define PLL_CTRL_8 0x0058
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#define PLL_CTRL_9 0x0059
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#define PLL_CTRL_A 0x005a
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#define PLL_CTRL_B 0x005b
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#define PLL_CTRL_C 0x005c
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#define PLL_CTRL_D 0x005d
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#define PLL_CTRL_E 0x005e
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#define PLL_CTRL_F 0x005f
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#define PLL_REM_0 0x0060
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#define PLL_REM_1 0x0061
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#define PLL_REM_2 0x0062
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#define PLL_DIV_0 0x0063
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#define PLL_DIV_1 0x0064
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#define PLL_DIV_2 0x0065
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#define PLL_FRAC_0 0x0066
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#define PLL_FRAC_1 0x0067
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#define PLL_FRAC_2 0x0068
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#define PLL_INT_0 0x0069
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#define PLL_INT_1 0x006a
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#define PLL_REF_DIV 0x006b
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#define PLL_SSC_P0 0x006c
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#define PLL_SSC_P1 0x006d
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#define PLL_SSC_P2 0x006e
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#define PLL_SSC_STEP0 0x006f
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#define PLL_SSC_STEP1 0x0070
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#define PLL_SSC_STEP2 0x0071
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#define PLL_SSC_OFFSET0 0x0072
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#define PLL_SSC_OFFSET1 0x0073
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#define PLL_SSC_OFFSET2 0x0074
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#define PLL_SSC_OFFSET3 0x0075
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#define GPIO_OEN 0x0079
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#define MIPI_CFG_PW 0x007a
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#define GPIO_0_SEL 0x007b
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#define GPIO_1_SEL 0x007c
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#define IRQ_SEL 0x007d
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#define DBG_SEL 0x007e
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#define DBG_SIGNAL 0x007f
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#define MIPI_ERR_VECTOR_L 0x0080
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#define MIPI_ERR_VECTOR_H 0x0081
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#define MIPI_ERR_VECTOR_EN_L 0x0082
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#define MIPI_ERR_VECTOR_EN_H 0x0083
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#define MIPI_MAX_SIZE_L 0x0084
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#define MIPI_MAX_SIZE_H 0x0085
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#define DSI_CTRL 0x0086
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#define MIPI_PN_SWAP 0x0087
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#define MIPI_SOT_SYNC_BIT_0 0x0088
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#define MIPI_SOT_SYNC_BIT_1 0x0089
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#define MIPI_ULPS_CTRL 0x008a
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#define MIPI_CLK_CHK_VAR 0x008e
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#define MIPI_CLK_CHK_INI 0x008f
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#define MIPI_T_TERM_EN 0x0090
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#define MIPI_T_HS_SETTLE 0x0091
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#define MIPI_T_TA_SURE_PRE 0x0092
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#define MIPI_T_LPX_SET 0x0094
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#define MIPI_T_CLK_MISS 0x0095
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#define MIPI_INIT_TIME_L 0x0096
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#define MIPI_INIT_TIME_H 0x0097
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#define MIPI_T_CLK_TERM_EN 0x0099
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#define MIPI_T_CLK_SETTLE 0x009a
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#define MIPI_TO_HS_RX_L 0x009e
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#define MIPI_TO_HS_RX_H 0x009f
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#define MIPI_PHY_0 0x00a0
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#define MIPI_PHY_1 0x00a1
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#define MIPI_PHY_2 0x00a2
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#define MIPI_PHY_3 0x00a3
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#define MIPI_PHY_4 0x00a4
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#define MIPI_PHY_5 0x00a5
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#define MIPI_PD_RX 0x00b0
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#define MIPI_PD_TERM 0x00b1
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#define MIPI_PD_HSRX 0x00b2
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#define MIPI_PD_LPTX 0x00b3
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#define MIPI_PD_LPRX 0x00b4
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#define MIPI_PD_CK_LANE 0x00b5
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#define MIPI_FORCE_0 0x00b6
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#define MIPI_RST_CTRL 0x00b7
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#define MIPI_RST_NUM 0x00b8
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#define MIPI_DBG_SET_0 0x00c0
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#define MIPI_DBG_SET_1 0x00c1
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#define MIPI_DBG_SET_2 0x00c2
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#define MIPI_DBG_SET_3 0x00c3
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#define MIPI_DBG_SET_4 0x00c4
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#define MIPI_DBG_SET_5 0x00c5
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#define MIPI_DBG_SET_6 0x00c6
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#define MIPI_DBG_SET_7 0x00c7
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#define MIPI_DBG_SET_8 0x00c8
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#define MIPI_DBG_SET_9 0x00c9
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#define MIPI_DBG_SEL 0x00e0
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#define MIPI_DBG_DATA 0x00e1
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#define MIPI_ATE_TEST_SEL 0x00e2
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#define MIPI_ATE_STATUS_0 0x00e3
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#define MIPI_ATE_STATUS_1 0x00e4
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#define ICN6211_MAX_REGISTER MIPI_ATE_STATUS_1
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struct icn6211 {
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struct drm_bridge base;
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struct drm_connector connector;
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struct drm_panel *panel;
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struct drm_bridge *bridge;
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struct drm_display_mode mode;
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struct device *dev;
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struct i2c_client *client;
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struct mipi_dsi_device dsi;
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struct regmap *regmap;
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struct clk *refclk; /* reference clock for RGB output clock */
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struct regulator *vdd1; /* MIPI RX power supply, can be 1.8V-3.3V */
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struct regulator *vdd2; /* PLL power supply, can be 1.8V-3.3V */
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struct regulator *vdd3; /* RGB output power supply, can be 1.8V-3.3V */
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struct gpio_desc *enable_gpio; /* When EN is low, this chip is reset */
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};
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static inline struct icn6211 *bridge_to_icn6211(struct drm_bridge *b)
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{
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return container_of(b, struct icn6211, base);
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}
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static inline struct icn6211 *connector_to_icn6211(struct drm_connector *c)
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{
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return container_of(c, struct icn6211, connector);
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}
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static enum drm_connector_status
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icn6211_connector_detect(struct drm_connector *connector, bool force)
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{
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return connector_status_connected;
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}
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static const struct drm_connector_funcs icn6211_connector_funcs = {
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.dpms = drm_atomic_helper_connector_dpms,
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.detect = icn6211_connector_detect,
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.fill_modes = drm_helper_probe_single_connector_modes,
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.destroy = drm_connector_cleanup,
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.reset = drm_atomic_helper_connector_reset,
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.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
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};
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static struct drm_encoder *
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icn6211_connector_best_encoder(struct drm_connector *connector)
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{
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struct icn6211 *icn6211 = connector_to_icn6211(connector);
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return icn6211->base.encoder;
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}
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static int icn6211_connector_get_modes(struct drm_connector *connector)
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{
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struct icn6211 *icn6211 = connector_to_icn6211(connector);
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return drm_panel_get_modes(icn6211->panel);
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}
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static const struct drm_connector_helper_funcs
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icn6211_connector_helper_funcs = {
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.get_modes = icn6211_connector_get_modes,
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.best_encoder = icn6211_connector_best_encoder,
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};
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static void icn6211_bridge_disable(struct drm_bridge *bridge)
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{
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struct icn6211 *icn6211 = bridge_to_icn6211(bridge);
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if (icn6211->panel)
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drm_panel_disable(icn6211->panel);
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}
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static void icn6211_bridge_enable(struct drm_bridge *bridge)
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{
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struct icn6211 *icn6211 = bridge_to_icn6211(bridge);
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if (icn6211->panel)
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drm_panel_enable(icn6211->panel);
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}
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static void icn6211_bridge_post_disable(struct drm_bridge *bridge)
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{
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struct icn6211 *icn6211 = bridge_to_icn6211(bridge);
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if (icn6211->panel)
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drm_panel_unprepare(icn6211->panel);
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if (icn6211->enable_gpio)
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gpiod_direction_output(icn6211->enable_gpio, 0);
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regulator_disable(icn6211->vdd3);
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regulator_disable(icn6211->vdd2);
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regulator_disable(icn6211->vdd1);
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clk_disable_unprepare(icn6211->refclk);
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}
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static void icn6211_bridge_pre_enable(struct drm_bridge *bridge)
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{
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struct icn6211 *icn6211 = bridge_to_icn6211(bridge);
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const struct drm_display_mode *mode = &icn6211->mode;
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u32 hactive, hfp, hsw, hbp, vactive, vfp, vsw, vbp;
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u8 hactive_l, hactive_h, hfp_l, hfp_h, hbp_l, hbp_h, hsw_l, hsw_h;
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u8 vactive_l, vactive_h;
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u32 device_id_h, device_id_l;
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u32 pll_refdiv, pll_extra_div, pll_dv, pll_int;
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unsigned long refclk = clk_get_rate(icn6211->refclk);
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int ret;
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clk_prepare_enable(icn6211->refclk);
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ret = regulator_enable(icn6211->vdd1);
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if (ret)
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dev_err(icn6211->dev,
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"failed to enable vdd1 supply: %d\n", ret);
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ret = regulator_enable(icn6211->vdd2);
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if (ret)
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dev_err(icn6211->dev,
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"failed to enable vdd2 supply: %d\n", ret);
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ret = regulator_enable(icn6211->vdd3);
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if (ret)
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dev_err(icn6211->dev,
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"failed to enable vdd3 supply: %d\n", ret);
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if (icn6211->enable_gpio)
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gpiod_direction_output(icn6211->enable_gpio, 1);
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usleep_range(10000, 11000);
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regmap_read(icn6211->regmap, DEVICE_ID_H, &device_id_h);
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regmap_read(icn6211->regmap, DEVICE_ID_L, &device_id_l);
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dev_info(icn6211->dev, "The ID of device: 0x%04x\n",
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(device_id_h << 8) | device_id_l);
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hactive = mode->hdisplay;
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hfp = mode->hsync_start - mode->hdisplay;
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hsw = mode->hsync_end - mode->hsync_start;
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hbp = mode->htotal - mode->hsync_end;
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vactive = mode->vdisplay;
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vfp = mode->vsync_start - mode->vdisplay;
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vsw = mode->vsync_end - mode->vsync_start;
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vbp = mode->vtotal - mode->vsync_end;
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hactive_l = hactive & 0xff;
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hactive_h = (hactive >> 8) & 0xf;
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vactive_l = vactive & 0xff;
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vactive_h = (vactive >> 8) & 0xf;
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hfp_l = hfp & 0xff;
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hfp_h = (hfp >> 8) & 0x3;
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hsw_l = hsw & 0xff;
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hsw_h = (hsw >> 8) & 0x3;
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hbp_l = hbp & 0xff;
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hbp_h = (hbp >> 8) & 0x3;
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regmap_write(icn6211->regmap, HACTIVE_L, hactive_l);
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regmap_write(icn6211->regmap, VACTIVE_L, vactive_l);
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regmap_write(icn6211->regmap, VACTIVE_HACTIVE_H,
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(vactive_h << 4) | hactive_h);
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regmap_write(icn6211->regmap, HFP_L, hfp_l);
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regmap_write(icn6211->regmap, HSW_L, hsw_l);
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regmap_write(icn6211->regmap, HBP_L, hbp_l);
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regmap_write(icn6211->regmap, HFP_HSW_HBP_H,
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(hfp_h << 4) | (hsw_h << 2) | hbp_h);
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regmap_write(icn6211->regmap, VFP, vfp);
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regmap_write(icn6211->regmap, VSW, vsw);
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regmap_write(icn6211->regmap, VBP, vbp);
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regmap_write(icn6211->regmap, SYNC_EVENT_DLY_LOW, 0x80);
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regmap_write(icn6211->regmap, HFP_MIN, hfp);
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regmap_write(icn6211->regmap, MIPI_PD_CK_LANE, 0xa0);
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regmap_write(icn6211->regmap, PLL_CTRL_C, 0xff);
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regmap_write(icn6211->regmap, BIST_POL, 0x01);
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regmap_write(icn6211->regmap, PLL_CTRL_6, 0x90);
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/*
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* FIXME:
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* fout = fin / pll_refdiv / pll_extra_div * pll_int / pll_dv / 2
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*/
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pll_refdiv = 1;
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pll_extra_div = 2;
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if (mode->clock <= 44000) {
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pll_dv = 8;
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regmap_write(icn6211->regmap, PLL_REF_DIV, 0x71);
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} else if (mode->clock <= 88000) {
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pll_dv = 4;
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regmap_write(icn6211->regmap, PLL_REF_DIV, 0x51);
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} else {
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pll_dv = 2;
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regmap_write(icn6211->regmap, PLL_REF_DIV, 0x31);
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}
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pll_int = DIV_ROUND_UP(mode->clock * 1000 * 2 * pll_dv,
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refclk / pll_refdiv / pll_extra_div);
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regmap_write(icn6211->regmap, PLL_INT_0, pll_int);
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dev_dbg(icn6211->dev,
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"pll_refdiv=%d, pll_extra_div=%d, pll_int=%d, pll_dv=%d\n",
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pll_refdiv, pll_extra_div, pll_int, pll_dv);
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dev_dbg(icn6211->dev, "fin=%ld, fout=%ld\n", refclk,
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refclk / pll_refdiv / pll_extra_div * pll_int / pll_dv / 2);
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/*
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* TODO:
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* RGB color swap mode
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* RGB_SWAP 000 001 010 011 100 101
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* Group_0 Red Red Green Green Blue Blue
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* Group_1 Green Blue Red Blue Red Green
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* Group_2 Blue Green Blue Red Green Red
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*
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* Data bit order mode
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* BIT_ORDER 000 001 010 011 100 101
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* Group_X[7] invalid invalid Color[5] Color[0] Color[7] Color[0]
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* Group_X[6] invalid invalid Color[4] Color[1] Color[6] Color[1]
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* Group_X[5] Color[5] Color[0] Color[3] Color[2] Color[5] Color[2]
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* Group_X[4] Color[4] Color[1] Color[2] Color[3] Color[4] Color[3]
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* Group_X[3] Color[3] Color[2] Color[1] Color[4] Color[3] Color[4]
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* Group_X[2] Color[2] Color[3] Color[0] Color[5] Color[2] Color[5]
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* Group_X[1] Color[1] Color[4] invaild invaild Color[1] Color[6]
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* Group_X[0] Color[0] Color[5] invaild invaild Color[0] Color[7]
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*
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* Note: Group_0[7:0] = DATA[7:0]
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* Group_1[7:0] = DATA[15:8]
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* Group_2[7:0] = DATA[23:16]
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*/
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regmap_write(icn6211->regmap, SYS_CTRL_0, 0x45);
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regmap_write(icn6211->regmap, SYS_CTRL_1, 0x88);
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regmap_write(icn6211->regmap, MIPI_FORCE_0, 0x20);
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regmap_write(icn6211->regmap, PLL_CTRL_1, 0x20);
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regmap_write(icn6211->regmap, CONFIG_FINISH, 0x10);
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if (icn6211->panel)
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drm_panel_prepare(icn6211->panel);
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}
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static void icn6211_bridge_mode_set(struct drm_bridge *bridge,
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struct drm_display_mode *mode,
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struct drm_display_mode *adj)
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{
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struct icn6211 *icn6211 = bridge_to_icn6211(bridge);
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drm_mode_copy(&icn6211->mode, adj);
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}
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static int icn6211_bridge_attach(struct drm_bridge *bridge)
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{
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struct icn6211 *icn6211 = bridge_to_icn6211(bridge);
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struct drm_connector *connector = &icn6211->connector;
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struct drm_device *drm = bridge->dev;
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struct mipi_dsi_host *host = bridge->driver_private;
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struct mipi_dsi_device *dsi = &icn6211->dsi;
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int ret;
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dsi->lanes = 4;
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dsi->channel = 0;
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dsi->format = MIPI_DSI_FMT_RGB888;
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dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
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MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET;
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dsi->host = host;
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ret = mipi_dsi_attach(dsi);
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if (ret) {
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dev_err(icn6211->dev, "failed to attach dsi host: %d\n", ret);
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return ret;
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}
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if (icn6211->bridge) {
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icn6211->bridge->encoder = bridge->encoder;
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ret = drm_bridge_attach(drm, icn6211->bridge);
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if (ret) {
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dev_err(icn6211->dev,
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"failed to attach bridge: %d\n", ret);
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return ret;
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}
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bridge->next = icn6211->bridge;
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} else {
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ret = drm_connector_init(drm, connector,
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&icn6211_connector_funcs,
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DRM_MODE_CONNECTOR_DPI);
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if (ret) {
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dev_err(icn6211->dev,
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"failed to initialize connector\n");
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return ret;
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}
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drm_connector_helper_add(connector,
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&icn6211_connector_helper_funcs);
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drm_mode_connector_attach_encoder(connector, bridge->encoder);
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drm_panel_attach(icn6211->panel, connector);
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}
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return 0;
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}
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static const struct drm_bridge_funcs icn6211_bridge_funcs = {
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.attach = icn6211_bridge_attach,
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.mode_set = icn6211_bridge_mode_set,
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.pre_enable = icn6211_bridge_pre_enable,
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.enable = icn6211_bridge_enable,
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.disable = icn6211_bridge_disable,
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.post_disable = icn6211_bridge_post_disable,
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};
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static const struct regmap_config icn6211_regmap_config = {
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.name = "icn6211",
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = ICN6211_MAX_REGISTER,
|
};
|
|
static int icn6211_i2c_probe(struct i2c_client *client,
|
const struct i2c_device_id *id)
|
{
|
struct device *dev = &client->dev;
|
struct icn6211 *icn6211;
|
int ret;
|
|
icn6211 = devm_kzalloc(dev, sizeof(*icn6211), GFP_KERNEL);
|
if (!icn6211)
|
return -ENOMEM;
|
|
icn6211->dev = dev;
|
icn6211->client = client;
|
i2c_set_clientdata(client, icn6211);
|
|
ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
|
&icn6211->panel, &icn6211->bridge);
|
if (ret)
|
return ret;
|
|
icn6211->refclk = devm_clk_get(dev, "refclk");
|
if (IS_ERR(icn6211->refclk)) {
|
ret = PTR_ERR(icn6211->refclk);
|
dev_err(dev, "failed to get ref clk: %d\n", ret);
|
return ret;
|
}
|
|
icn6211->vdd1 = devm_regulator_get(dev, "vdd1");
|
if (IS_ERR(icn6211->vdd1))
|
return PTR_ERR(icn6211->vdd1);
|
|
icn6211->vdd2 = devm_regulator_get(dev, "vdd2");
|
if (IS_ERR(icn6211->vdd2))
|
return PTR_ERR(icn6211->vdd2);
|
|
icn6211->vdd3 = devm_regulator_get(dev, "vdd3");
|
if (IS_ERR(icn6211->vdd3))
|
return PTR_ERR(icn6211->vdd3);
|
|
icn6211->enable_gpio = devm_gpiod_get_optional(dev, "enable", 0);
|
if (IS_ERR(icn6211->enable_gpio)) {
|
ret = PTR_ERR(icn6211->enable_gpio);
|
dev_err(dev, "failed to request enable GPIO: %d\n", ret);
|
return ret;
|
}
|
|
icn6211->regmap = devm_regmap_init_i2c(client, &icn6211_regmap_config);
|
if (IS_ERR(icn6211->regmap)) {
|
ret = PTR_ERR(icn6211->regmap);
|
dev_err(dev, "failed to initialize regmap: %d\n", ret);
|
return ret;
|
}
|
|
icn6211->base.funcs = &icn6211_bridge_funcs;
|
icn6211->base.of_node = dev->of_node;
|
ret = drm_bridge_add(&icn6211->base);
|
if (ret) {
|
dev_err(dev, "failed to add drm_bridge: %d\n", ret);
|
return ret;
|
}
|
|
return 0;
|
}
|
|
static int icn6211_i2c_remove(struct i2c_client *client)
|
{
|
struct icn6211 *icn6211 = i2c_get_clientdata(client);
|
|
drm_bridge_remove(&icn6211->base);
|
|
return 0;
|
}
|
|
static const struct i2c_device_id icn6211_i2c_table[] = {
|
{ "icn6211", 0 },
|
{}
|
};
|
MODULE_DEVICE_TABLE(i2c, icn6211_i2c_table);
|
|
static const struct of_device_id icn6211_of_match[] = {
|
{ .compatible = "chipone,icn6211" },
|
{}
|
};
|
MODULE_DEVICE_TABLE(of, icn6211_of_match);
|
|
static struct i2c_driver icn6211_i2c_driver = {
|
.driver = {
|
.name = "icn6211",
|
.of_match_table = icn6211_of_match,
|
},
|
.probe = icn6211_i2c_probe,
|
.remove = icn6211_i2c_remove,
|
.id_table = icn6211_i2c_table,
|
};
|
module_i2c_driver(icn6211_i2c_driver);
|
|
MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
|
MODULE_DESCRIPTION("Chipone ICN6211 MIPI-DSI to RGB bridge chip driver");
|
MODULE_LICENSE("GPL v2");
|
