/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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/*
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* Pre-requisites: headers required by header of this unit
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*/
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#include "include/i2caux_interface.h"
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#include "engine.h"
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#include "i2c_engine.h"
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/*
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* Header of this unit
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*/
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#include "i2c_sw_engine.h"
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/*
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* Post-requisites: headers required by this unit
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*/
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/*
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* This unit
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*/
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#define SCL false
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#define SDA true
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static inline bool read_bit_from_ddc(
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struct ddc *ddc,
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bool data_nor_clock)
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{
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uint32_t value = 0;
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if (data_nor_clock)
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dal_gpio_get_value(ddc->pin_data, &value);
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else
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dal_gpio_get_value(ddc->pin_clock, &value);
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return (value != 0);
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}
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static inline void write_bit_to_ddc(
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struct ddc *ddc,
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bool data_nor_clock,
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bool bit)
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{
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uint32_t value = bit ? 1 : 0;
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if (data_nor_clock)
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dal_gpio_set_value(ddc->pin_data, value);
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else
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dal_gpio_set_value(ddc->pin_clock, value);
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}
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static bool wait_for_scl_high(
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struct dc_context *ctx,
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struct ddc *ddc,
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uint16_t clock_delay_div_4)
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{
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uint32_t scl_retry = 0;
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uint32_t scl_retry_max = I2C_SW_TIMEOUT_DELAY / clock_delay_div_4;
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udelay(clock_delay_div_4);
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/* 3 milliseconds delay
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* to wake up some displays from "low power" state.
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*/
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do {
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if (read_bit_from_ddc(ddc, SCL))
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return true;
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udelay(clock_delay_div_4);
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++scl_retry;
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} while (scl_retry <= scl_retry_max);
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return false;
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}
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static bool start_sync(
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struct dc_context *ctx,
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struct ddc *ddc_handle,
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uint16_t clock_delay_div_4)
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{
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uint32_t retry = 0;
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/* The I2C communications start signal is:
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* the SDA going low from high, while the SCL is high. */
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write_bit_to_ddc(ddc_handle, SCL, true);
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udelay(clock_delay_div_4);
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do {
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write_bit_to_ddc(ddc_handle, SDA, true);
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if (!read_bit_from_ddc(ddc_handle, SDA)) {
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++retry;
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continue;
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}
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SCL, true);
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if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
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break;
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write_bit_to_ddc(ddc_handle, SDA, false);
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SCL, false);
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udelay(clock_delay_div_4);
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return true;
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} while (retry <= I2C_SW_RETRIES);
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return false;
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}
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static bool stop_sync(
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struct dc_context *ctx,
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struct ddc *ddc_handle,
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uint16_t clock_delay_div_4)
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{
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uint32_t retry = 0;
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/* The I2C communications stop signal is:
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* the SDA going high from low, while the SCL is high. */
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write_bit_to_ddc(ddc_handle, SCL, false);
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SDA, false);
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SCL, true);
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if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
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return false;
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write_bit_to_ddc(ddc_handle, SDA, true);
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do {
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udelay(clock_delay_div_4);
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if (read_bit_from_ddc(ddc_handle, SDA))
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return true;
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++retry;
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} while (retry <= 2);
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return false;
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}
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static bool write_byte(
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struct dc_context *ctx,
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struct ddc *ddc_handle,
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uint16_t clock_delay_div_4,
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uint8_t byte)
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{
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int32_t shift = 7;
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bool ack;
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/* bits are transmitted serially, starting from MSB */
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do {
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SDA, (byte >> shift) & 1);
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SCL, true);
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if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
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return false;
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write_bit_to_ddc(ddc_handle, SCL, false);
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--shift;
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} while (shift >= 0);
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/* The display sends ACK by preventing the SDA from going high
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* after the SCL pulse we use to send our last data bit.
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* If the SDA goes high after that bit, it's a NACK */
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SDA, true);
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SCL, true);
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if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
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return false;
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/* read ACK bit */
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ack = !read_bit_from_ddc(ddc_handle, SDA);
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udelay(clock_delay_div_4 << 1);
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write_bit_to_ddc(ddc_handle, SCL, false);
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udelay(clock_delay_div_4 << 1);
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return ack;
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}
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static bool read_byte(
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struct dc_context *ctx,
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struct ddc *ddc_handle,
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uint16_t clock_delay_div_4,
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uint8_t *byte,
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bool more)
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{
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int32_t shift = 7;
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uint8_t data = 0;
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/* The data bits are read from MSB to LSB;
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* bit is read while SCL is high */
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do {
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write_bit_to_ddc(ddc_handle, SCL, true);
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if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
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return false;
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if (read_bit_from_ddc(ddc_handle, SDA))
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data |= (1 << shift);
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write_bit_to_ddc(ddc_handle, SCL, false);
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udelay(clock_delay_div_4 << 1);
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--shift;
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} while (shift >= 0);
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/* read only whole byte */
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*byte = data;
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udelay(clock_delay_div_4);
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/* send the acknowledge bit:
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* SDA low means ACK, SDA high means NACK */
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write_bit_to_ddc(ddc_handle, SDA, !more);
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SCL, true);
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if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
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return false;
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write_bit_to_ddc(ddc_handle, SCL, false);
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SDA, true);
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udelay(clock_delay_div_4);
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return true;
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}
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static bool i2c_write(
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struct dc_context *ctx,
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struct ddc *ddc_handle,
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uint16_t clock_delay_div_4,
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uint8_t address,
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uint32_t length,
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const uint8_t *data)
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{
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uint32_t i = 0;
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if (!write_byte(ctx, ddc_handle, clock_delay_div_4, address))
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return false;
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while (i < length) {
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if (!write_byte(ctx, ddc_handle, clock_delay_div_4, data[i]))
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return false;
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++i;
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}
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return true;
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}
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static bool i2c_read(
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struct dc_context *ctx,
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struct ddc *ddc_handle,
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uint16_t clock_delay_div_4,
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uint8_t address,
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uint32_t length,
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uint8_t *data)
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{
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uint32_t i = 0;
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if (!write_byte(ctx, ddc_handle, clock_delay_div_4, address))
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return false;
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while (i < length) {
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if (!read_byte(ctx, ddc_handle, clock_delay_div_4, data + i,
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i < length - 1))
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return false;
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++i;
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}
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return true;
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}
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/*
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* @brief
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* Cast 'struct i2c_engine *'
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* to 'struct i2c_sw_engine *'
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*/
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#define FROM_I2C_ENGINE(ptr) \
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container_of((ptr), struct i2c_sw_engine, base)
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/*
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* @brief
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* Cast 'struct engine *'
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* to 'struct i2c_sw_engine *'
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*/
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#define FROM_ENGINE(ptr) \
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FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
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enum i2caux_engine_type dal_i2c_sw_engine_get_engine_type(
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const struct engine *engine)
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{
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return I2CAUX_ENGINE_TYPE_I2C_SW;
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}
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bool dal_i2c_sw_engine_submit_request(
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struct engine *engine,
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struct i2caux_transaction_request *i2caux_request,
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bool middle_of_transaction)
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{
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struct i2c_sw_engine *sw_engine = FROM_ENGINE(engine);
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struct i2c_engine *base = &sw_engine->base;
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struct i2c_request_transaction_data request;
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bool operation_succeeded = false;
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if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
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request.action = middle_of_transaction ?
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I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT :
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I2CAUX_TRANSACTION_ACTION_I2C_READ;
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else if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
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request.action = middle_of_transaction ?
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I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT :
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I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
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else {
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i2caux_request->status =
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I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION;
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/* in DAL2, there was no "return false" */
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return false;
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}
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request.address = (uint8_t)i2caux_request->payload.address;
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request.length = i2caux_request->payload.length;
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request.data = i2caux_request->payload.data;
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base->funcs->submit_channel_request(base, &request);
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if ((request.status == I2C_CHANNEL_OPERATION_ENGINE_BUSY) ||
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(request.status == I2C_CHANNEL_OPERATION_FAILED))
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i2caux_request->status =
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I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY;
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else {
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enum i2c_channel_operation_result operation_result;
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do {
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operation_result =
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base->funcs->get_channel_status(base, NULL);
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switch (operation_result) {
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case I2C_CHANNEL_OPERATION_SUCCEEDED:
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i2caux_request->status =
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I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
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operation_succeeded = true;
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break;
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case I2C_CHANNEL_OPERATION_NO_RESPONSE:
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i2caux_request->status =
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I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
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break;
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case I2C_CHANNEL_OPERATION_TIMEOUT:
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i2caux_request->status =
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I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
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break;
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case I2C_CHANNEL_OPERATION_FAILED:
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i2caux_request->status =
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I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE;
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break;
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default:
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i2caux_request->status =
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I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION;
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break;
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}
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} while (operation_result == I2C_CHANNEL_OPERATION_ENGINE_BUSY);
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}
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return operation_succeeded;
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}
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uint32_t dal_i2c_sw_engine_get_speed(
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const struct i2c_engine *engine)
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{
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return FROM_I2C_ENGINE(engine)->speed;
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}
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void dal_i2c_sw_engine_set_speed(
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struct i2c_engine *engine,
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uint32_t speed)
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{
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struct i2c_sw_engine *sw_engine = FROM_I2C_ENGINE(engine);
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ASSERT(speed);
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sw_engine->speed = speed ? speed : I2CAUX_DEFAULT_I2C_SW_SPEED;
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sw_engine->clock_delay = 1000 / sw_engine->speed;
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if (sw_engine->clock_delay < 12)
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sw_engine->clock_delay = 12;
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}
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bool dal_i2caux_i2c_sw_engine_acquire_engine(
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struct i2c_engine *engine,
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struct ddc *ddc)
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{
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enum gpio_result result;
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result = dal_ddc_open(ddc, GPIO_MODE_FAST_OUTPUT,
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GPIO_DDC_CONFIG_TYPE_MODE_I2C);
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if (result != GPIO_RESULT_OK)
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return false;
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engine->base.ddc = ddc;
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return true;
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}
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void dal_i2c_sw_engine_submit_channel_request(
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struct i2c_engine *engine,
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struct i2c_request_transaction_data *req)
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{
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struct i2c_sw_engine *sw_engine = FROM_I2C_ENGINE(engine);
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struct ddc *ddc = engine->base.ddc;
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uint16_t clock_delay_div_4 = sw_engine->clock_delay >> 2;
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/* send sync (start / repeated start) */
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bool result = start_sync(engine->base.ctx, ddc, clock_delay_div_4);
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/* process payload */
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if (result) {
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switch (req->action) {
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case I2CAUX_TRANSACTION_ACTION_I2C_WRITE:
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case I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT:
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result = i2c_write(engine->base.ctx, ddc, clock_delay_div_4,
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req->address, req->length, req->data);
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break;
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case I2CAUX_TRANSACTION_ACTION_I2C_READ:
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case I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT:
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result = i2c_read(engine->base.ctx, ddc, clock_delay_div_4,
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req->address, req->length, req->data);
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break;
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default:
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result = false;
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break;
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}
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}
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/* send stop if not 'mot' or operation failed */
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if (!result ||
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(req->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
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(req->action == I2CAUX_TRANSACTION_ACTION_I2C_READ))
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if (!stop_sync(engine->base.ctx, ddc, clock_delay_div_4))
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result = false;
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req->status = result ?
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I2C_CHANNEL_OPERATION_SUCCEEDED :
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I2C_CHANNEL_OPERATION_FAILED;
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}
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enum i2c_channel_operation_result dal_i2c_sw_engine_get_channel_status(
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struct i2c_engine *engine,
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uint8_t *returned_bytes)
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{
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/* No arbitration with VBIOS is performed since DCE 6.0 */
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return I2C_CHANNEL_OPERATION_SUCCEEDED;
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}
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void dal_i2c_sw_engine_destruct(
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struct i2c_sw_engine *engine)
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{
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dal_i2c_engine_destruct(&engine->base);
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}
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static void destroy(
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struct i2c_engine **ptr)
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{
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dal_i2c_sw_engine_destruct(FROM_I2C_ENGINE(*ptr));
|
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kfree(*ptr);
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*ptr = NULL;
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}
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static const struct i2c_engine_funcs i2c_engine_funcs = {
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.acquire_engine = dal_i2caux_i2c_sw_engine_acquire_engine,
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.destroy = destroy,
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.get_speed = dal_i2c_sw_engine_get_speed,
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.set_speed = dal_i2c_sw_engine_set_speed,
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.setup_engine = dal_i2c_engine_setup_i2c_engine,
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.submit_channel_request = dal_i2c_sw_engine_submit_channel_request,
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.process_channel_reply = dal_i2c_engine_process_channel_reply,
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.get_channel_status = dal_i2c_sw_engine_get_channel_status,
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};
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static void release_engine(
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struct engine *engine)
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{
|
|
}
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static const struct engine_funcs engine_funcs = {
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.release_engine = release_engine,
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.get_engine_type = dal_i2c_sw_engine_get_engine_type,
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.acquire = dal_i2c_engine_acquire,
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.submit_request = dal_i2c_sw_engine_submit_request,
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};
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void dal_i2c_sw_engine_construct(
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struct i2c_sw_engine *engine,
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const struct i2c_sw_engine_create_arg *arg)
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{
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dal_i2c_engine_construct(&engine->base, arg->ctx);
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dal_i2c_sw_engine_set_speed(&engine->base, arg->default_speed);
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engine->base.funcs = &i2c_engine_funcs;
|
engine->base.base.funcs = &engine_funcs;
|
}
|
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struct i2c_engine *dal_i2c_sw_engine_create(
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const struct i2c_sw_engine_create_arg *arg)
|
{
|
struct i2c_sw_engine *engine;
|
|
if (!arg) {
|
BREAK_TO_DEBUGGER();
|
return NULL;
|
}
|
|
engine = kzalloc(sizeof(struct i2c_sw_engine), GFP_KERNEL);
|
|
if (!engine) {
|
BREAK_TO_DEBUGGER();
|
return NULL;
|
}
|
|
dal_i2c_sw_engine_construct(engine, arg);
|
return &engine->base;
|
}
|
